参数资料
型号: HIP6004ECVZ-T
厂商: Intersil
文件页数: 10/13页
文件大小: 0K
描述: IC CTRLR PWM VOLTAGE MON 20TSSOP
标准包装: 2,500
应用: 控制器,Intel VRM8.5
输入电压: 5V,12V
输出数: 1
输出电压: 1.05 V ~ 1.825 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
HIP6004E
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
+12V
V CC
+5V OR LESS
P UPPER = Io 2 x r DS(ON) x D +
1 Io x V
2
IN x t SW x F S
HIP6004E
BOOT
P LOWER = Io 2 x r DS(ON) x (1 - D)
Where: D is the duty cycle = V OUT / V IN ,
t SW is the switch ON time, and
UGATE
PHASE
Q 1
NOTE:
V G-S ≈ V CC -5V
F S is the switching frequency.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004E. However, logic-level gate MOSFETs
-
+
LGATE
PGND
GND
Q 2
D 2
NOTE:
V G-S ≈ V CC
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V CC . The boot capacitor, C BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V CC
less the boot diode drop (V D ) when the lower MOSFET, Q 2
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
+12V
D BOOT
FIGURE 10. UPPER GATE DRIVE - DIRECT V CC DRIVE OPTION
VCC
+ V D -
BOOT
+5V OR +12V
HIP6004E
UGATE
PHASE
C BOOT
Q1
NOTE:
V G-S ≈ V CC -V D
-
+
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ V CC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to V CC . This option should only be used in
converter systems where the main input voltage is +5V DC or
less. The peak upper gate-to-source voltage is approximately
V CC less the input supply. For +5V main power and +12V DC
for the bias, the gate-to-source voltage of Q 1 is 7V. A logic-
level MOSFET is a good choice for Q 1 and a logic-level
MOSFET can be used for Q 2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V CC .
10
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