参数资料
型号: HIP6004ECVZ-T
厂商: Intersil
文件页数: 5/13页
文件大小: 0K
描述: IC CTRLR PWM VOLTAGE MON 20TSSOP
标准包装: 2,500
应用: 控制器,Intel VRM8.5
输入电压: 5V,12V
输出数: 1
输出电压: 1.05 V ~ 1.825 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
HIP6004E
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R T ) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft-start interval with
C SS = 0.1 μ F. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t 1 in Figure 3, the
SS voltage reaches the valley of the oscillator’s triangle wave.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t 2 . With sufficient
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t 2 and t 3 in Figure 3.
At t 3 the SS voltage exceeds the DACOUT voltage and the
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ± 10% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
Fs ≈ 200kHz + ---------------------
6
5 x 10
R T ( k ? )
(R T to GND)
0V
PGOOD
(2V/DIV.)
Conversely, connecting a pull-up resistor (R T ) from this pin to
V CC reduces the switching frequency according to the
following equation:
SOFT-START
(1V/DIV.)
OUTPUT
VOLTAGE
Fs ≈ 200kHz – ---------------------
7
4 x 10
R T ( k ? )
(R T to 12V)
0V
0V
t 1
t 2
t 3
(1V/DIV.)
TIME (5ms/DIV.)
FIGURE 3. SOFT START INTERVAL
RT pin has a constant voltage of 1.26V typically.
Functional Description
Initialization
The HIP6004E automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (V IN ) on the OCSET pin. The level on
OCSET is equal to V IN less a fixed voltage drop (see over-
current protection). The POR function initiates soft-start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V IN
and V CC are equivalent and the +12V power source must
exceed the rising VCC threshold before POR initiates operation.
Soft Start
The POR function initiates the soft-start sequence. An internal
10 μ A current source charges an external capacitor (C SS ) on
5
Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, r DS(ON)
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
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