参数资料
| 型号： | HIP6007CB-T |
| 厂商： | Intersil |
| 文件页数： | 7/10页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM STD BUCK 14-SOIC |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel Pentium? Pro、PowerP、Alpha |
| 输入电压： | 2.5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 1.27 V ~ 12 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 管件 |
HIP6007
DRIVER
F P1 = ------------------------------------------------------
F Z1 = ---------------------------------
2 π ? R2 ? ----------------------
F P2 = ---------------------------------
F Z2 = -----------------------------------------------------
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V E/A ) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of Vin at the
PHASE node. The PWM wave is smoothed by the output
filter (Lo and Co).
V IN
OSC
180 o . The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1 1
2 π ? R2 ? C1 C1 ? C2
C1 + C2
1 1
2 π ? ( R1 + R3 ) ? C3 2 π ? R3 ? C3
-
? V OSC
PWM
COMPARATOR
+
DRIVER
L O
PHASE
C O
ESR
(PARASITIC)
V OUT
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter’s Double Pole
(~75% F LC )
3. Place 2 ND Zero at Filter’s Double Pole
4. Place 1 ST Pole at the ESR Zero
Z FB
5. Place 2 ND Pole at Half the Switching Frequency
-
V E/A
+
ERROR
AMP
Z IN
REFERENCE
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not
DETAILED COMPENSATION COMPONENTS
shown in Figure 8. Using the above guidelines should give a
C1
C2
R2
Z FB
C3
Z IN
R3
V OUT
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
COMP
-
+
FB
R1
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
HIP6007
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45 o .
Include worst case component variations when determining
phase margin.
function of Vout/V E/A . This function is dominated by a DC
Gain and the output filter (Lo and Co), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
the modulator is simply the input voltage (Vin) divided by the
peak-to-peak oscillator voltage ? V OSC .
100
80
60
F Z1 F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
Modulator Break Frequency Equations
40
20LOG
F LC = ---------------------------------------
F ESR = --------------------------------------------
1 1
2 π ? L O ? C O 2 π ? ( ESR ? C O )
The compensation network consists of the error amplifier
(internal to the HIP6007) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
20
0
-20
-40
-60
(R2/R1)
MODULATOR
GAIN
10 100 1K
F LC
10K
20LOG
(V IN / ? V OSC )
F ESR
100K 1M 10M
COMPENSATION
GAIN
CLOSED LOOP
GAIN
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
137
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
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