- 您现在的位置：买卖IC网 > PDF目录385382 > HIP6016 (Intersil Corporation) FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN PDF资料下载
参数资料
| 型号： | HIP6016 |
| 厂商： | Intersil Corporation |
| 元件分类： | FPGA |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 先进的双PWM和线性功率控制 |
| 文件页数： | 9/14页 |
| 文件大小： | 130K |
| 代理商： | HIP6016 |
2-204
Resistor R
OCSET
programs the over-current trip level for the
PWM converter. As shown in Figure 9, the internal 200
μ
A
current sink develops a voltage across R
OCSET
(V
SET
) that is
referenced to V
IN
. The DRIVE signal enables the over-current
comparator (OVER-CURRENT1). When the voltage across the
upper MOSFET (V
DS(ON)
) exceeds V
SET
, the over-current
comparator trips to set the over-current latch. Both V
SET
and
V
DS
are referenced to V
IN
and a small capacitor across
R
OCSET
helps V
OCSET
track the variations of V
IN
due to
MOSFET switching. The over-current function will trip at a peak
inductor current (I
PEAK)
determined by:
The OC trip point varies with MOSFETs’ temperature. To avoid
over-current tripping in the normal operating load range,
determine the R
OCSET
resistor from the equation above with:
1. The maximum r
DS(ON)
at the highest junction
temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for I
PEAK
> I
OUT(MAX)
+ (
I)/2, where
I is the output inductor ripple current.
For an equation for the output inductor ripple current see
the section under component guidelines titled ‘Output
Inductor Selection’.
OUT1 Voltage Program
The output voltage of the PWM converter is programmed to
discrete levels between 1.3V
DC
and 3.5V
DC
. This output is
designed to supply the microprocessor core voltage. The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) through a TTL-compatible 5-bit
digital-to-analog converter. The level of DACOUT also sets
the PGOOD and OVP thresholds. Table 1 specifies the
DACOUT voltage for the different combinations of
connections on the VID pins. The VID pins can be left open
for a logic 1 input, because they are internally pulled up to
+5V by a 10
μ
A (typically) current source. Changing the VID
inputs during operation is not recommended. The sudden
change in the resulting reference voltage could toggle the
PGOOD signal and exercise the over-voltage protection.
‘11111’ VID pin combination results in an INHIBIT, which
disables the IC and the open-collector at the PGOOD pin.
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s
output of the PWM converter. After the output voltage
increases to approximately 80% of the set value, the
reference input of the error amplifier is clamped to a voltage
proportional to the SS pin voltage. Both linear outputs follow
a similar start-up sequence. The resulting output voltage
sequence is shown in Figure 6.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval is
programmed by the soft-start capacitor, C
SS
. Programming
a faster soft-start interval increases the peak surge current.
The peak surge current occurs during the initial output
voltage rise to 80% of the set value.
IPEAK=
IOCSrDS ON
ROCSET
)
×
(
TABLE 1. V
OUT1
VOLTAGE PROGRAM
PIN NAME
NOMINAL
OUT1
VOLTAGE
DACOUT
VID4
VID3
VID2
VID1
VID0
0
1
1
1
1
1.30
0
1
1
1
0
1.35
0
1
1
0
1
1.40
0
1
1
0
0
1.45
0
1
0
1
1
1.50
0
1
0
1
0
1.55
0
1
0
0
1
1.60
0
1
0
0
0
1.65
0
0
1
1
1
1.70
0
0
1
1
0
1.75
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
INHIBIT
1
1
1
1
0
2.1
1
1
1
0
1
2.2
1
1
1
0
0
2.3
1
1
0
1
1
2.4
1
1
0
1
0
2.5
1
1
0
0
1
2.6
1
1
0
0
0
2.7
1
0
1
1
1
2.8
1
0
1
1
0
2.9
1
0
1
0
1
3.0
1
0
1
0
0
3.1
1
0
0
1
1
3.2
1
0
0
1
0
3.3
1
0
0
0
1
3.4
1
0
0
0
0
3.5
NOTE: 0 = connected to GND or V
SS
, 1 = open or connected to 5V
through pull-up resistors.
HIP6016
相关PDF资料 |
PDF描述 |
|---|---|
| HIP6016CB | Advanced PWM and Dual Linear Power Control |
| HIP6017B | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6017BCB | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6018B | 100,000 System Gate FPGA - NOT RECOMMENDED for NEW DESIGN |
| HIP6018BCB | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6016 WAF | 制造商:Intersil Corporation 功能描述: |
| HIP6016CB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP6016CB WAF | 制造商:Harris Corporation 功能描述: |
| HIP6016CB-T | 制造商:Rochester Electronics LLC 功能描述:ADVANCED PWM & CONTROL "3 IN 1"& 1.5V OUTPUTS T&R - Bulk |
| HIP6017 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Dual Linear Power Control |
发布紧急采购，3分钟左右您将得到回复。