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| 型号： | HIP6019BEVAL1 |
| 厂商： | Intersil |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR HIP6019B |
| 标准包装： | 1 |
| 系列： | * |
HIP6019B
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the only component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has switching losses, since the lower device turns
L O × I TRAN
V IN – V OUT
L O × I TRAN
t FALL = -------------------------------
t RISE = --------------------------------
V OUT
on into near zero voltage.
The equations below assume linear voltage-current
I O × r DS ( ON ) × V OUT
I O × V IN × t SW × F
P UPPER = ------------------------------------------------------------ + ---------------------------------------------------- S
V IN
I O × r DS ( ON ) × ( V IN – V OUT )
P LOWER = ---------------------------------------------------------------------------------
where: I TRAN is the transient load current step, t RISE is the
response time to the application of load, and t FALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are proportional to the switching frequency
(F S ) and are dissipated by the HIP6019B, thus not
contributing to the MOSFETs’ temperature rise. However,
large gate charge increases the switching interval, t SW
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
2
2
2
V IN
The r DS(ON) is different for the two previous equations even
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately V CC less the
input supply. For +5V main power and +12V DC for the bias,
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12V DC . A logic-level MOSFET is a good choice
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V CC .
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
+12V
V CC
+5V OR LESS
MOSFET Selection/Considerations
The HIP6019B requires 4 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of PWM1 converter. PWM2 converter uses a
HIP6019B
UGATE
PHASE
Q1
NOTE:
V GS ≈ V CC -5V
MOSFET as the buck switch and the linear controller drives
a MOSFET as a pass transistor. These should be selected
based upon r DS(ON) , gate supply requirements, and thermal
management requirements.
-
+
LGATE
PGND
Q2
CR1
NOTE:
V GS ≈ V CC
GND
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
13
FIGURE 14. OUTPUT GATE DRIVERS
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the
lower MOSFET and the turn on of the upper MOSFET. The
FN4587.1
April 13, 2005
相关PDF资料 |
PDF描述 |
|---|---|
| HIP6021EVAL1 | EVALUATION BOARD HIP6021 |
| HIP6301EVAL2 | EVALUATION BOARD HIP6301 |
| HIP6302EVAL1 | EVALUATION BOARD HIP6302 |
| HIP6521EVAL1 | EVALUATION BOARD HIP6521 |
| HIP6602BCR-T | IC DRVR MOSF 2CH SYC BUCK 16-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6019CB | 制造商:Harris Corporation 功能描述: |
| HIP6019CB-T | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP6019EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Control |
| HIP6020 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
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