参数资料
型号: HIP6020
厂商: Intersil Corporation
元件分类: FPGA
英文描述: FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 先进的双PWM和线性双电源控制器
文件页数: 12/15页
文件大小: 139K
代理商: HIP6020
2-292
where
L
OUT(MIN)
- minimum output inductor value at full output
current
ESR
OUT
- equivalent ESR of the output capacitor bank
BW - desired converter bandwidth (not to exceed 0.25 to
0.30 of the switching frequency)
The design procedure for this output should follow the
following steps:
1. Choosenumberandtypeofoutputcapacitorstomeetthe
output transient requirements based on the dynamic
loading characteristics of the output.
2. Determine the equivalent ESR of the output capacitor
bank and calculate minimum output inductor value.
3. Verify that chosen inductor meets this minimum value
criteria (at full output load). It is recommended the cho-
sen output inductor be no more than 30% saturated at
full output load.
Oscillator Synchronization
The PWM controllers use a triangle wave for comparison
with the error amplifier output to provide a pulse-width
modulated signal. Should the output voltage of the two
converters be programmed close to each other, then cross-
talk between the converters could cause non-uniform
PHASE pulse-widths and increased output voltage ripple.
The HIP6020 avoids this problem by synchronizing the two
converters 180 degrees out of phase for output voltage
settings within the same range. Therefore, for both output
voltage settings less than 2.4V or both output voltage
settings greater or equal to 2.4V, PWM1 operates out of
phase with PWM2. For one PWM output voltage setting
below 2.4V and the other PWM output voltage setting of
2.4V and above, PWM1 operates in phase with PWM2.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates
above 1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Linear Output Capacitors
The output capacitors for the linear regulators provide
dynamic load current. Thus capacitors C
OUT3
and C
OUT4
should be selected for transient load regulation.
PWM Output Inductor Selection
Each PWM converter requires an output inductor. The
output inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. Additionally, PWM2 output inductor has to
meet the minimum value criteria for loop stability as
described in paragraph ‘
PWM2 Controller Feedback
Compensation
’. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values increase
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6020 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.
I
V
-------------------------------
V
S
V
IN
---------------
×
=
V
OUT
I
ESR
×
=
HIP6020
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