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参数资料
| 型号： | HIP6020 |
| 厂商： | Intersil Corporation |
| 元件分类： | FPGA |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 先进的双PWM和线性双电源控制器 |
| 文件页数： | 6/15页 |
| 文件大小： | 139K |
| 代理商： | HIP6020 |
2-286
SS (Pin 12)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28
μ
A current source, sets the
soft-start interval of the converter.
FAULT / RT (Pin 13)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
T
) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Conversely, connecting a pull-up resistor (R
T
) from this pin
to VCC reduces the switching frequency according to the
following equation:
Nominally, the voltage at this pin is 1.26V. In the event of an
over-voltage or over-current condition, this pin is internally
pulled to VCC.
PGOOD (Pin 8)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within
±
10% of the
DACOUT reference voltage or when any of the other outputs
are below their under-voltage thresholds.
The PGOOD output is open for ‘11111’ VID code.
VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)
VID0-4 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage, as well as the
coresponding PGOOD and OVP thresholds.
OCSET1, OCSET2 (Pins 23 and 9)
Connect a resistor (R
OCSET
) from this pin to the drain of the
respective upper MOSFET. R
OCSET
, an internal 200
μ
A
current source (I
OCSET
), and the upper MOSFET’s on-
resistance (r
DS(ON)
) set the converter over-current (OC) trip
point according to the following equation:
I
DS ON
)
An over-current trip cycles the soft-start function.
The voltage at OCSET1 pin is monitored for power-on reset
(POR) purposes.
PHASE1, PHASE2 (Pins 26 and 2)
Connect the PHASE pins to the respective PWM converter’s
upper MOSFET source. These pins represent the gate drive
return current path and are used to monitor the voltage drop
across the upper MOSFETs for over-current protection.
UGATE1, UGATE2 (Pins 27 and 1)
Connect UGATE pins to the respective PWM converter’s
upper MOSFET gate. These pins provide the gate drive for
the upper MOSFETs.
LGATE1 (Pin 25)
Connect LGATE1 to the synchronous PWM converter’s
lower MOSFET gate. This pin provides the gate drive for the
lower MOSFET.
COMP1 and FB1 (Pins 20, and 21)
COMP1 and FB1 are the available external pins of the
synchronous PWM regulator error amplifier. The FB1 pin is
the inverting input of the error amplifier. Similarly, the
COMP1 pin is the error amplifier output. These pins are
used to compensate the voltage-mode control feedback loop
of the synchronous PWM converter.
VSEN1 (Pin 22)
This pin is connected to the synchronous PWM converters’
output voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status and for over-
voltage protection.
VSEN2 (Pin 10)
Connect this pin to the output of the standard buck PWM
regulator. The voltage at this pin is regulated to the level
predetermined by the logic-level status of the SELECT pin.
This pin is also monitored by the PGOOD comparator circuit.
SELECT (Pin 11)
This pin determines the output voltage of the AGP bus
switching regulator. A low TTL input sets the output voltage
to 1.5V, while a high input sets the output voltage to 3.3V.
DRIVE3 (Pin 18)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.5V regulator’s pass transistor.
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for undervoltage events.
DRIVE4 (Pin 15)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.8V regulator’s pass transistor.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.
Description
Operation
The HIP6020 monitors and precisely controls 4 output voltage
levels (Refer to Figures 1, 2, and 3). It is designed for
microprocessor computer applications with 3.3V, 5V, and 12V
bias input from an ATX power supply. The IC has 2 PWM and
Fs
200KHz
T
6
)
--------------------
+
≈
(R
T
to GND)
Fs
200KHz
T
7
)
--------------------
–
≈
(R
T
to 12V)
I
PEAK
R
×
---------------------------------------------------
=
HIP6020
相关PDF资料 |
PDF描述 |
|---|---|
| HIP6020CB | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6301VCBZ-T | 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| HIP6301VCBZA | Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller |
| HIP6301VCBZA-T | 150000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| HIP6301V | Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6020A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020A_01 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020ACB | 制造商:Intersil Corporation 功能描述: |
| HIP6020ACB WAF | 制造商:Harris Corporation 功能描述: |
| HIP6020ACB-T | 制造商:Rochester Electronics LLC 功能描述:DUAL PWM AND 2 LINEAR CONTROLLER W/O VID=11111 SHUTDOWN - Tape and Reel |
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