参数资料
型号: HIP6301VCB-T
厂商: Intersil
文件页数: 19/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-SOIC
标准包装: 1,000
PWM 型: 控制器
输出数: 4
频率 - 最大: 336kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
HIP6301V, HIP6302V
Small Outline Plastic Packages (SOIC)
N
M16.15 (JEDEC MS-012-AC ISSUE C)
INDEX
AREA
E
H
0.25(0.010) M
B M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
-B-
SYMBOL
A
MIN
0.0532
MAX
0.0688
MIN
1.35
MAX
1.75
NOTES
-
1
2
3
L
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
SEATING PLANE
C
0.0075
0.0098
0.19
0.25
-
-A-
D
A
h x 45°
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
-C-
α
e
0.050 BSC
1.27 BSC
-
e
B
0.25(0.010) M
C A M
B S
A1
0.10(0.004)
C
H
h
L
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
5
6
N
16
16
7
NOTES:
α
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
19
Rev. 1 6/05
FN9034.3
May 5, 2008
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