参数资料
型号: HIP6302CBZA
厂商: Intersil
文件页数: 3/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-SOIC
标准包装: 480
PWM 型: 控制器
输出数: 2
频率 - 最大: 305kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
HIP6302
Simplified Power System Diagram
VSEN
HIP6302
PWM 1
PWM 2
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
SYNCHRONOUS
MICROPROCESSOR
RECTIFIED BUCK
CHANNEL
VID
Functional Pin Description
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
16 V CC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
pin.
VSEN (Pin 10)
Power good monitor input. Connect to the microprocessor-
CORE voltage.
ISEN2 (Pin 11) and ISEN1 (Pin 14)
Current sense inputs from the individual converter channel’s
phase nodes.
PWM2 (Pin 12) and PWM1 (Pin 13)
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)
and VID0 (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The HIP6302 decodes
VID bits to establish the output voltage. See Table 1.
COMP (Pin 6)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
FB (Pin 7)
Inverting input of the internal error amplifier.
FS/DIS (Pin 8)
Channel frequency, F SW , select and disable. A resistor from
this pin to ground sets the switching frequency of the
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
3
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of a HIP6601/2/3 driver.
PGOOD (Pin 15)
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage (VSEN pin) is within specified
limits and Soft-Start has timed out.
V CC (Pin 16)
Bias supply. Connect this pin to a 5V supply.
FN4766.3
December 27, 2004
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