参数资料
型号: HIP6311ACBZA-T
厂商: Intersil
文件页数: 11/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-SOIC
标准包装: 1,000
PWM 型: 控制器
输出数: 4
频率 - 最大: 1.5MHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
HIP6311A
R IN
R FB
C c
FB
COMP
HIP6311A
V IN
ERROR
AMPLIFIER
-
SAWTOOTH
GENERATOR
CORRECTION
+
COMPARATOR
-
+
PWM
CIRCUIT
PWM
HIP6601
Q1
L 01
I L
V CORE
+
-
Q2
PHASE
REFERENCE
DAC
DIFFERENCE
+
CURRENT
I SEN
R ISEN
SENSING
-
ONLY ONE OUTPUT
TO OTHER
CHANNELS
AVERAGING
CURRENT
SENSING
FROM
OTHER
CHANNELS
STAGE SHOWN
INDUCTOR
CURRENT(S)
FROM
OTHER
TO OVER
CURRENT
TRIP
+
-
COMPARATOR
REFERENCE
CHANNELS
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
Current Sensing and Balancing
Overview
The HIP6311A samples the on-state voltage drop across
each synchronous rectifier FET, Q2, as an indication of the
inductor current in that phase, see Figure 7. Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r DS(ON) (Q2) x inductor current (I L ). Note that I L , the
inductor current, is either 1/2, 1/3, or 1/4 of the total current
(I LT ), depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
R ISEN resistor to develop the I ISEN current to the HIP6311A
ISEN pin. This pin is held at virtual ground, so the current
through R ISEN is I L x r DS(ON) (Q2) / R ISEN .
The I ISEN current provides information to perform the
following functions:
1. Detection of an over-current condition
2. Reduce the regulator output voltage with increasing load
current (droop)
3. Balance the I L currents in multiple channels
Over-Current, Selecting R ISEN
The current detected through the R ISEN resistor is averaged
with the current(s) detected in the other 1, 2, or 3 channels. The
11
averaged current is compared with a trimmed, internally gener-
ated current, and used to detect an over-current condition.
The nominal current through the R ISEN resistor should be
50 μ A at full output load current, and the nominal trip point for
over-current detection is 165% of that value, or 82.5 μ A.
Therefore, R ISEN = I L x r DS(ON) (Q2) / 50 μ A.
For a full load of 25A per phase, and an r DS(ON) (Q2) of
4m ? , R ISEN = 2k ? .
The over-current trip point would be 165% of 25A, or ~ 41A
per phase. The R ISEN value can be adjusted to change the
over-current trip point, but it is suggested to stay within ± 25%
of nominal.
Droop, Selection of R IN
The average of the currents detected through the R ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R IN , so the average
current creates a voltage drop across R IN . This drop
increases the apparent V CORE voltage with increasing load
current, causing the system to decrease V CORE to maintain
balance at the FB pin. This is the desired “droop” voltage used
to maintain V CORE within limits under transient conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
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