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参数资料
| 型号： | HMC6352-DEMO |
| 厂商： | Honeywell Microelectronics & Precision Sensors |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | DEMONSTRATION BOARD FOR HMC6352 |
| 标准包装： | 1 |
| 类型： | 数字罗盘 |
| 适用于相关产品： | HMC6352 |
| 所含物品： | 演示板 |
| 其它名称： | 342-1069 |
From Figure 1, the host microprocessor ( μ P) controls the HMC6352 via I C serial data interface lines for data (SDA) and
HMC6352
If the HMC6352 is stored in an uncontrolled humidity environment (>10% RH) beyond one week, a 24-hour bakeout
period should be implemented before solder reflow. This bakeout should be in accordance with JEDEC J-STD-033A at
125°C for MSL3 devices.
Three heating zones are defined in SMT reflow soldering process; the preheating zone, the soaking zone, and the reflow
zone. The preheating zone includes the soaking zone, and nominally ranges from 2 to 4 minutes depending on
temperature rise to arrive in the 160°C to 180°C soaking plateau to active the flux and remove any remaining moisture in
the assembly. Preheat rise times must not exceed 3°C per second to avoid moisture and mechanical stresses that result
in “popcorning” the package encapsulation.
The soaking zone is a one to two minute temperature stabilization time to bring the all the PCB assembly to an even
temperature. Typically this zone has a 0.5 to 0.6°C rise in temperature heading towards the main reflow heating elements.
The reflow zone is 30 to 90 second bump in temperature over the 180°C point to reflow the screened solder paste before
a gradual cooling. The peak temperature is typically in the 230°C to 240°C range.
It should be noted that lead-free solders tend to require higher peak reflow temperatures and longer reflow times. Cooling
zone temperature fall should decrease not more than 6°C per second to avoid mechanical stresses in the PCB assembly.
REFERENCE DESIGN
The schematic diagram in Figure 1 shows the basic HMC6352 application circuit with a minimum of external components.
2
clock (SCL). Two external 10k-ohm pull-up resistors to the nominal +3 volt DC supply create normally high logic states
when the interface lines are not in use. The host initiates use of the interface by creating the 100 kHz clock and pulling low
the data line to indicate the start condition. The data line logic state transitions are only allowed during the clock low states
and require the data line to be stable in the high states, with the exception of the start and stop conditions.
Figure 1
Reference Design Schematic
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