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参数资料
| 型号： | HSC-ADC-EVALB-DCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL ADC FIFO DUAL-CH USB HS |
| 设计资源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 标准包装： | 1 |
| 附件类型： | ADC 接口板 |
| 适用于相关产品： | 双路模数转换器型 |
| 产品目录页面： | 781 (CN2011-ZH PDF) |
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HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
The SPI interface designed on the Cypress IC can communicate
with up to five different SPI-enabled devices. The CLK and data
lines are common to all SPI devices. The correct device is
chosen to communicate by using one of the five active low chip
select pins. This functionality is controlled by selecting a SPI
channel in the software.
CLOCKING WITH INTERLEAVED DATA
ADCs with very high data rates can exceed the capability of a
single buffer memory channel (~133 MSPS). These converters
often demultiplex the data into two channels to reduce the rate
required to capture the data. In these applications, ADC Analyzer
must interleave the data from both channels to process it as a
single channel. The user can configure the software to process
the first sample from Channel A, the second from Channel B,
CONNECTING TO THE DEMUX BRD
ADCs that have parallel LVDS outputs require another board
that is connected between the ADC evaluation board and the
FIFO data capture card. This board converts parallel LVDS to
parallel CMOS, using both channels of the FIFO data capture
card. For more detailed information on this board, send an
email to highspeed.converters@analog.com
UPGRADING FIFO MEMORY
The FIFO evaluation board includes one or two 32 kB FIFOs
that are capable of 133 MHz clock signals, depending on the
model number. Pin-compatible FIFO upgrades are available
from IDT. See Table 2 for the IDT part number matrix.
Table 2. IDT Part Number Matrix
and so on, or vice versa. The synchronization circuit included in
the buffer memory forces a small delay between the write enable
signals (WENA and WENB) to the FIFO memory chips (Pin 1,
U101, and U201), ensuring that the data is captured in one
FIFO before the other. Jumper J401 and Jumper J402 determine
which FIFO receives WENA and which FIFO receives WENB.
CONNECTING TO THE HSC-ADC-FPGA-4/-8
ADCs that have serial LVDS outputs require another board that
is connected between the ADC evaluation board and the FIFO
Part Number
IDT72V283-L7-5PF (Default )
IDT72V293-L7-5PF
IDT72V2103-L7-5PF
IDT72V2113-L7-5PF
IDT72V283-L6PF
IDT72V293-L6PF
IDT72V2103-L6PF
IDT72V2113-L6PF
FIFO Depth
32 kB
64 kB
132 kB
256 kB
32 kB
64 kB
132 kB
256 kB
FIFO Speed
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
166 MHz
166 MHz
166 MHz
data capture card. This board converts the serial data into
For more information, visit www.idt.com.
parallel CMOS so that the FIFO data capture card can accept
the data. For more detailed information on this board, refer to
the HSC-ADC-FPGA datasheet at www.analog.com/hsc-FIFO .
Rev. 0 | Page 10 of 28
相关PDF资料 |
PDF描述 |
|---|---|
| HSC-ADC-EVALCZ | KIT EVAL ADC FIFO HI SPEED |
| HSHM-GUIDE-PIN-4 | CONN GUIDE PIN 8-32 UNC-2A |
| HSHM-GUIDE-SOCKET-1 | CONN HSHM GUIDE SOCKET 1 |
| HTC-10M | FUSEBLOCK 250V FOR 5X20 FUSE UL |
| HV275C | GAS TUBE GDT 3KA 2750V CORE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HSC-ADC-EVALB-SC | 制造商:Analog Devices 功能描述:FPGA BOARD FOR HSC ADCS - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| HSC-ADC-EVALCZ | 功能描述:KIT EVAL ADC FIFO HI SPEED RoHS:是 类别:编程器，开发系统 >> 配件 系列:- 标准包装:1 系列:- 附件类型:适配器板 适用于相关产品:RCB230，RCB231，RCB212 配用:26790D-ND - RCB BREAKOUT BOARD RS232 CABLE |
| HSC-ADC-EVALCZ | 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| HSC-ADC-EVALDZ | 功能描述:数据转换 IC 开发工具 Data Converter Evaluation Platform RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| HSC-ADC-EVAL-SC | 制造商:Analog Devices 功能描述:FIFO BOARD FOR HSC A-D CONVERTERS - Bulk 制造商:Analog Devices 功能描述:EVALUTION KITSINGLE CHANNEL ((NS)) |
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