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参数资料
| 型号： | HW-PC4 |
| 厂商： | Xilinx Inc |
| 文件页数： | 6/9页 |
| 文件大小： | 0K |
| 描述： | CABLE PROGRAMMING FOR XILINX DEV |
| 产品变化通告： | Development Systems Discontinuation 11/Jan/2010 |
| 标准包装： | 1 |
| 附件类型： | 编程缆线 |
| 适用于相关产品： | Xilinx FPGA、CPLDS、平台闪存 PROM、XC18V00 PROM、系统 ACE MPM |
| 其它名称： | 122-1276 HW-PC4-ND |
R
TDO/MISO Timing Specifications
When using JTAG or SPI configuration mode, target
systems must guarantee that TDO/MISO signal assertion
meets a minimum setup time relative to the positive edge of
TCK/SCK. Buffers or multiplexers in the target hardware
can add phase delays as long as the following setup
specification is not violated. Figure 6 illustrates the
relationship between TCK/SCK and TDO/MISO_internal for
the 5 MHz default PC4 configuration speed.
TDO/MISO_internal is the propagation delayed version of
the TDO/MISO signal generated by the target device
(accounting for any target system buffers, multiplexers, and
distributed capacitance).
All PC4 output signal transitions and input signal latching
events are synchronized to an internal 40 MHz system
clock. In JTAG mode, TDO is asserted by the last device in
.
X-Ref Target - Figure 6
Xilinx Parallel Cable IV
the target JTAG chain on the negative edge of TCK (1 in
on the negative edge of SCK (1 in Figure 6 ). Setup and hold
times for TDO/MISO_internal are referenced to the next
positive edge of TCK/SCK (2 in Figure 6 ).
When the PC4 is operating at the maximum clock frequency
of 5 MHz, the TDO/MISO_internal is sampled 12.5 ns (4 in
time (T DOS , 3 in Figure 6 ) is specified relative to the positive
edge of TCK/SCK (2 in Figure 6 ).
When the PC4 configuration clock rate is changed to a
lower frequency, there is additional margin for propagation
delay through target buffers. Any design that complies with
the margins specified for 5 MHz operation is guaranteed to
operate at lower frequencies.
1
(1)
2
3
4
TCK/ S CK
TM S / SS
TDI/MI S O
TDO/MI S O_intern a l
T DO S (2)
Notes:
T DOH
1. Target device asserts TDO/MISO after the negative edge of TCK/SCK.
2. TDO/MISO_internal must be stable here.
Figure 6: TDO/MISO Timing Diagram
Table 3: TDO/MISO Timing Specifications
D S 097_09_111606
Selected Frequency
5 MHz
200 kHz
Symbol
T DOS
T DOH
T DOS
T DOH
Parameter
TDO/MISO setup time
TDO/MISO hold time
TDO/MISO setup time
TDO/MISO hold time
Min
–42
88
–2442
2488
Max
–
–
–
–
Units
ns
ns
ns
ns
DS097 (v2.5) May 14, 2008
Product Specification
6
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