- 您现在的位置：买卖IC网 > PDF目录223992 > HY27US081G1MTCS (HYNIX SEMICONDUCTOR INC) 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 PDF资料下载
参数资料
| 型号： | HY27US081G1MTCS |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 |
| 封装： | 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48 |
| 文件页数： | 4/39页 |
| 文件大小： | 312K |
| 代理商： | HY27US081G1MTCS |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页
Rev 0.2 / May. 2007
12
Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address
loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block address loading
initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
The block address loading is accomplished in four cycles depending on the device density. Only block addresses (A14 to
A26) are needed while A9 to A13 is ignored. At the rising edge of WE after the erase confirm command input, the inter-
nal Program Erase Controller handles erase and erase-verify. When the erase operation is completed, the Write Status
Bit (I/O 0) may be checked. Figure_16 details the sequence.
3.4 Copy-Back Program.
The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to
another page within the same plane without using an external memory. Since the time-consuming sequential-reading
and its reloading cycles are removed, the system performance is improved. The benefit is especially obvious when a
portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The
operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and
copying-program with the address of destination page. A normal read operation with "00h" command and the address
of the source page moves the whole 528byte data into the internal buffer. As soon as the device returns to Ready state,
Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Pro-
gram Confirm command (10h) is required to actually begin the programming operation.
Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished,
any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the
same between source and target page
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the use
of Copy-Back operation."
Figure 15 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
- 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 3
bus cycles to input the source page address.) This operation copies all 264 Words/ 528 Bytes from the page into
the page Buffer.
- 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
given with the 4cycles to input the target page address. A26, A25 must be the same for the Source and Target
Pages.
- 3. Then the confirm command is issued to start the P/E/R Controller.
Note:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page (source page) to an
even address page (target page) or from an even address page (source page) to an odd address page (target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
相关PDF资料 |
PDF描述 |
|---|---|
| HY27US081G1MTPMP | 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 |
| HY5116100BJ-70 | 16M X 1 FAST PAGE DRAM, 70 ns, PDSO24 |
| HY5116804CSLT-80 | 2M X 8 EDO DRAM, 80 ns, PDSO28 |
| HY514400ALT-60 | 1M X 4 FAST PAGE DRAM, 60 ns, PDSO20 |
| HY51VS65173HGLT-5 | 4M X 16 EDO DRAM, 50 ns, PDSO50 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY27US08281A | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Memory |
| HY27US08282A | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Memory |
| HY27US08561A | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
| HY27US08561A-T (P) | 制造商:SK Hynix Inc 功能描述: |
| HY27US08561M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
发布紧急采购，3分钟左右您将得到回复。