参数资料
型号: HY29LV320BF-80
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 32 Mbit (2M x 16) Low Voltage Flash Memory
中文描述: 2M X 16 FLASH 3V PROM, 80 ns, PBGA63
封装: 7 X 11 MM, FBGA-63
文件页数: 25/44页
文件大小: 323K
代理商: HY29LV320BF-80
25
r1.3/May 02
HY29LV320
and ignores the command for the specified sec-
tors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or
0
to
1
for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is as-
serted low.
Figure 9 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be read
at any address, and is valid after the rising edge
of the final WE# pulse in the Program or Erase
command sequence, including during the sector
erase time-out. The system may use either OE#
or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode) cause
DQ[6] to toggle. DQ[6] stops toggling when the op-
eration is complete. If a program address falls within
Table 14. Write and Erase Operation Status Summary
1
e
d
o
M
n
o
r
e
p
O
e
o
n
g
n
m
m
a
o
P
e
m
o
c
g
n
m
m
a
o
P
s
s
e
o
n
e
s
a
E
d
e
m
o
c
e
s
a
E
s
e
s
a
n
w
d
a
e
R
r
e
s
a
o
n
n
w
d
a
e
R
r
e
s
d
e
d
n
e
p
s
u
s
e
o
n
g
n
m
m
a
o
P
e
m
o
c
g
n
m
m
a
o
P
Notes:
1. A valid address is required when reading status information (except RY/BY#). For a programming operation, the ad-
dress used for the read cycle should be the program address. For an erase operation, the address used for the read
cycle should be any address within a non-protected sector marked for erasure (any address within a non-protected
sector for the chip erase operation).
2. DQ[5] status switches to a
1
when a program or erase operation exceeds the maximum timing limit.
3. A
1
during sector erase indicates that the 50 μs time-out has expired and active erasure is in progress. DQ[3] is not
applicable to the chip erase operation.
4. Equivalent to
No Toggle
because data is obtained in this state.
5. Data (DQ[7:0]) = 0xFF immediately after erasure.
6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).
]
Q
#
Q
a
D
0
a
D
D
D
]
Q
e
g
o
T
a
D
e
g
o
T
a
D
D
]
Q
1
a
D
1
a
D
D
]
Q
A
/
N
a
D
1
3
a
D
D
]
Q
A
/
N
a
D
e
g
o
T
a
D
D
#
Y
B
/
0
1
0
1
Y
R
l
m
r
N
s
s
d
2
4
2
5
4
4
e
n
s
e
a
E
s
u
S
d
p
d
e
d
n
e
p
s
u
1
e
g
o
o
N
0
A
/
N
e
g
o
T
1
e
s
a
D
a
D
a
D
a
D
a
D
1
s
s
d
6
#
Q
a
D
D
e
g
a
D
o
T
1
a
D
2
A
/
a
D
N
A
/
a
D
N
0
1
6
4
a protected sector, DQ[6] toggles for approximately
1 μs after the program command sequence is writ-
ten, then returns to reading array data.
While the Automatic Erase algorithm is operating,
successive read cycles at any address cause
DQ[6] to toggle. DQ[6] stops toggling when the
erase operation is complete or when the device is
placed in the Erase Suspend mode. The host may
use DQ[2] to determine which sectors are erasing
or erase-suspended (see below). After an Erase
command sequence is written, if all sectors se-
lected for erasing are protected, DQ[6] toggles for
approximately 100 μs, then returns to reading ar-
ray data. If at least one selected sector is not
protected, the Automatic Erase algorithm erases
the unprotected sectors, and ignores the selected
sectors that are protected.
DQ[2] - Toggle Bit II
Toggle Bit II, DQ[2], when used with DQ[6], indi-
cates whether a particular sector is actively eras-
ing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
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