参数资料
型号: HY29LV320BF-80
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 32 Mbit (2M x 16) Low Voltage Flash Memory
中文描述: 2M X 16 FLASH 3V PROM, 80 ns, PBGA63
封装: 7 X 11 MM, FBGA-63
文件页数: 27/44页
文件大小: 323K
代理商: HY29LV320BF-80
27
r1.3/May 02
HY29LV320
Read DQ[7:0]
at Valid Address (Note 1)
DQ[6] Toggled
NO
(Note 3)
YES
PROGRAM/ERASE
COMPLETE
DQ[5] = 1
NO
YES
Read DQ[7:0]
at Valid Address (Note 1)
DQ[6] Toggled
(Note 2)
NO
YES
PROGRAM/ERASE
EXCEEDED TIME ERROR
Notes
:
1. During programming, the program address.
During sector erase, an address within any sector scheduled for erasure.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
Read DQ[7:0]
at Valid Address (Note 1)
START
Read DQ[7:0]
DQ[2] Toggled
NO
SECTOR BEING READ
IS IN ERASE SUSPEND
Read DQ[7:0]
YES
NO
(Note 4)
SECTOR BEING READ
IS NOT IN ERASE SUSPEND
Figure 10. Toggle Bit I and II Test Algorithm
HARDWARE DATA PROTECTION
The HY29LV320 provides several methods of pro-
tection to prevent accidental erasure or program-
ming which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 9. This
provides data protection against inadvertent writes.
Low V
CC
Write Inhibit
To protect data during V
CC
power-up and power-
down, the device does not accept write cycles
when V
CC
is less than V
LKO
(typically 2.4 volts). The
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until V
CC
is greater
than V
LKO
. The system must provide the proper
signals to the control pins to prevent unintentional
writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = V
IL
, CE# = V
IH
, or
WE# = V
IH
. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is auto-
matically reset to the Read mode on power-up.
Sector Protection
Additional data protection is provided by the
HY29LV320
s sector protect feature, described
previously, which can be used to protect sensitive
areas of the Flash array from accidental or unau-
thorized attempts to alter the data.
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