参数资料
型号: HY57V643220D
厂商: Hynix Semiconductor Inc.
英文描述: 4Banks x 512K x 32bits Synchronous DRAM
中文描述: 4Banks x为512k × 32位同步DRAM
文件页数: 11/13页
文件大小: 227K
代理商: HY57V643220D
Rev. 0.3 / Sep. 2004
11
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note :
1. A new command can be given t
RC
after self refresh exit.
Parameter
Sym-
bol
45
5
55
6
7
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS
Cycle Time
Operation
t
RC
58.5
-
55
-
55
-
60
-
63
-
ns
RAS
Cycle Time
Auto Refresh
t
RRC
58.5
-
55
-
55
-
60
-
63
-
ns
RAS to CAS Delay
t
RCD
18
-
15
-
16.5
-
18
-
20
-
ns
RAS Active Time
t
RAS
40.5 100K 38.7 100K 38.7 100K
42
100K
42
100K
ns
RAS Precharge Time
t
RP
18
-
15
-
16.5
-
18
-
20
-
ns
RAS to RAS Bank Active
Delay
t
RRD
9
-
10
-
11
-
12
-
14
-
ns
CAS to CAS Delay
t
CCD
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to
Data-In Delay
t
WTL
0
-
0
-
0
-
0
-
0
-
CLK
Data-in to Precharge
Command
t
DPL
TBD
-
TBD
-
TBD
-
1
-
1
-
CLK
Data-In to Active Command
t
DAL
t
DPL
+ t
RP
DQM to Data-Out Hi-Z
t
DQZ
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
t
DQM
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
t
MRD
2
-
2
-
2
-
2
-
2
-
CLK
Precharge to
Data Output
High-Z
CAS
Latency=3
t
PROZ3
3
-
3
-
3
-
3
-
3
-
CLK
CAS
Latency=2
t
PROZ2
-
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
t
DPE
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
t
SRE
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
t
REF
-
64
-
64
-
64
-
64
-
64
ms
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HY57V643220DTP-55 4Banks x 512K x 32bits Synchronous DRAM
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HY57V643220DLT-6 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM
HY57V643220DLT-7 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM