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参数资料
| 型号： | HY5DV651622TC-G55 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件页数： | 17/27页 |
| 文件大小： | 273K |
| 代理商： | HY5DV651622TC-G55 |
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Rev. 0.3/May. 02
17
HY5DV281622AT
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
RFU
DR
TM
CAS Latency
BT
Burst Length
A2
A1
A0
Burst Length
Sequential
Interleave
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
A3
Burst Type
0
Sequential
1
Interleave
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
A7
Test Mode
0
Normal
1
Test
A8
DLL Reset
0
No
1
Yes
BA0
MRS Type
0
MRS
1
EMRS
相关PDF资料 |
PDF描述 |
|---|---|
| HY5DV651622TC-G6 | DDR Synchronous DRAM |
| HY5DV651622TC-G7 | DDR Synchronous DRAM |
| HY5DV651622T-G55 | DDR Synchronous DRAM |
| HY5DV651622T-G6 | DDR Synchronous DRAM |
| HY5DV651622T-G7 | DDR Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DV651622TC-G6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622TC-G7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622T-G55 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622T-G6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622T-G7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
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