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参数资料
| 型号： | HY5DV651622TC-G55 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件页数： | 5/27页 |
| 文件大小： | 273K |
| 代理商： | HY5DV651622TC-G55 |
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Rev. 0.3/May. 02
5
HY5DV281622AT
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
LDM, UDM
Input
Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corre-
sponds to the data on DQ8-Q15.
LDQS, UDQS
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
DQ0 ~ DQ15
I/O
Data input / output pin : Data Bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
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PDF描述 |
|---|---|
| HY5DV651622TC-G6 | DDR Synchronous DRAM |
| HY5DV651622TC-G7 | DDR Synchronous DRAM |
| HY5DV651622T-G55 | DDR Synchronous DRAM |
| HY5DV651622T-G6 | DDR Synchronous DRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DV651622TC-G6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622TC-G7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622T-G55 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622T-G6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
| HY5DV651622T-G7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Synchronous DRAM |
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