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参数资料
| 型号： | HY5PS12823LF |
| 英文描述： | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II内存- 512M |
| 文件页数： | 14/66页 |
| 文件大小： | 862K |
| 代理商： | HY5PS12823LF |
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Rev. 0.52/Nov. 02 14
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
Note
Extended Mode Register Set
H
H
L
L
L
L
OP code
1,2
Mode Register Set
H
H
L
L
L
L
OP code
1,2
Device Deselect
H
X
H
X
X
X
X
1
No Operation
L
H
H
H
Bank Active
H
H
L
L
H
H
RA
V
1
Read
H
H
L
H
L
H
CA
L
V
1
Read with Autoprecharge
H
1,3
Write
H
H
L
H
L
L
CA
L
V
1
Write with Autoprecharge
H
1,4
Precharge All Banks
H
H
L
L
H
L
X
H
X
1,5
Precharge selected Bank
L
V
1
Auto Refresh
H
H
L
L
L
H
X
1
Self Refresh
Entry
H
L
L
L
L
H
X
1
Exit
L
H
H
X
X
X
1
L
H
H
H
Power Down
Mode
Entry
H
L
H
X
X
X
X
1
L
H
H
H
1
Exit
L
H
H
X
X
X
1
L
H
H
H
1
Note :
1. All DDR II commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Registers.
3. Burst reads or writes at BL=4 cannot be terminated. See sections “Reads interrupted by a Read” and “Write interrupted by a
Write” in 3.2.4 for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements outlined in section
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
Section
6. “X” means “H or L(but a defined logic level)”.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
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