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参数资料
| 型号： | HY5PS1G821LM-C4 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 128M X 8 DDR DRAM, 0.5 ns, PBGA63 |
| 封装： | FBGA-63 |
| 文件页数： | 64/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G821LM-C4 |
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Rev. 0.2 / Oct. 2005
64
1
HY5PS12421(L)M
HY5PS12821(L)M
5.3 Output Buffer Levels
5.3.1 Output AC Test Conditions
5.3.2 Output DC Current Drive
5.3.3 OCD defalut characteristics
Note 1: Absolute Specifications (0°C
≤
T
CASE
≤
+95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol
must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and
voltage.
Note 4: Slew rate measured from vil(ac) to vih(ac).
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew
rate as measured from AC to AC. This is guaranteed by design and characterization.
Note 6: DRAM output slew rate specification Table.
Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
Symbol
Parameter
SSTL_18 Class II
Units
Notes
V
OH
Minimum Required Output Pull-up under AC Test Load
V
TT
+ 0.603
V
V
OL
Maximum Required Output Pull-down under AC Test Load
V
TT
- 0.603
V
V
OTR
Output Timing Measurement Reference Level
0.5 * V
DDQ
V
1
1. The VDDQ of the device under test is referenced.
Symbol
Parameter
SSTl_18 Class II
Units
Notes
I
OH(dc)
Output Minimum Source DC Current
- 13.4
mA
1, 3, 4
I
OL(dc)
Output Minimum Sink DC Current
13.4
mA
2, 3, 4
1.
V
DDQ
= 1.7 V; V
OUT
= 1420 mV. (V
OUT
- V
DDQ
)/I
OH
must be less than 21 ohm for values of V
OUT
between V
DDQ
and V
DDQ
- 280
mV.
V
DDQ
= 1.7 V; V
OUT
= 280 mV. V
OUT
/I
OL
must be less than 21 ohm for values of V
OUT
between 0 V and 280 mV.
The dc value of V
REF
applied to the receiving device is set to V
TT
The values of I
OH(dc)
and I
OL(dc)
are based on the conditions given in Notes 1 and 2. They are used to test device drive current
capability to ensure V
IH
min plus a noise margin and V
IL
max minus a noise margin are delivered to an SSTL_18 receiver. The
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.
2.
3.
4.
Description
Output impedance
Pull-up and pull-
down mismatch
Output slew rate
Parameter
Min
12.6
Nom
18
Max
23.4
Unit
ohms
Notes
1,2
0
4
ohms
1,2,3
Sout
1.5
-
5
V/ns
1,4,5,6,7
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相关代理商/技术参数 |
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| HY5PS1G821LM-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
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| HY5PS1G821M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
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