IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions
,
continued
04 May 2007
Copyright
2007
EN21070504-00
www.Innovasic.com
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Pin
Signal
Name
PLCC
QFP
Description
ste
a3/ad3/
ste
43
37
s
ynchronization
t
ransmission
e
nable. Input. Serial interface Mode.
The logic level at the
ste
pin enables the transmission of the
synchronization bytes through the IA82527
miso
pin while the master
device transmits the Address and Control Byte as follows:
When a logic 0 is placed on the
ste
pin, the synchronization
bytes sent through the
miso
pin are 00H and 00H.
When a logic 1 is placed on the
ste
pin, the synchronization
bytes sent through the
miso
pin are AAH and 55H.
The IA82527 sends the synchronization bytes after the
cs_n
signal
has been asserted (low).
Transmit (
tx
), lines
0
and
1
. Output (push-pull).
Pins
tx0
and
tx1
are the outputs from the IA82527 to the Controller
Area Network (CAN) bus lines.
During a recessive bit,
tx0
is high and
tx1
is low. During a dominant
bit,
tx0
is low and
tx1
is high.
Power (
V
CC
).
This pin provides power for the IA82527 device. It must be
connected to a +5V DC power source.
Reference Voltage, ISO Physical Layer (
V
CC
/2
). Output.
The
V
CC
/2
pin provides a reference voltage for the ISO low-speed
physical layer:
2.
38V DC (minimum) to 2.60V DC (maximum)
(V
CC
= +5.00V; I
OUT
≤ 75 μA)
This pin only functions as
V
CC
/2
when the MUX bit of the CPU
Interface Register (02H) is 1.
Ground, Digital (
V
SS1
).
This pin provides the digital ground (0V) for the IA82527. It must be
connected to a V
SS
board plane.
Ground, Analog (
V
SS2
).
This pin provides the ground (0V) for the IA82527 analog comparator.
It must be connected to a V
SS
board plane.
tx0
—
26
20
tx1
—
25
19
V
CC
—
1
39
V
CC
/2
int_n/
V
CC
/2
24
18
V
SS1
—
23
17
V
SS2
—
20
14
continued
. . .