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| 型号： | IA82527-PTQ44A-R |
| 厂商： | Innovasic Semiconductor |
| 英文描述： | Serial Communications Controller CAN Protocol |
| 中文描述： | 串行通信控制器的CAN协议 |
| 文件页数： | 27/45页 |
| 文件大小： | 1760K |
| 代理商： | IA82527-PTQ44A-R |
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IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Table 8. Mode 0 and Mode 1 General Bus and
ready
Timing
04 May 2007
Copyright
2007
EN21070504-00
www.Innovasic.com
Customer Support:
Page 27 of 45
1-888-824-4184
Symbol
Parameter
Minimum
Maximum
1/t
XTAL
1/t
SCLK
1/t
MCLK
t
AVLL
t
LLAX
t
LHLL
t
LLRL
t
CLLL
t
QVWH
t
WHQX
t
WLWH
t
WHLH
t
WHCH
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to
ale
Low
Address Hold after
ale
Low
ale
High Time
ale
Low to
rd_n
Low
cs_n
Low to
ale
Low
Data Setup to
wr_n
or
wrh_n
High
Input Data Hold after
wr_n
or
wrh_n
High
wr_n
or
wrh_n
Pulse Width
wr_n
or
wrh_n
High to Next ale High
wr_n
or
wrh_n
High to
cs_n
High
rd_n
Pulse Width
This time is long enough to initiate a double read
cycle by loading the High Speed Registers (04H,
05H), but is too short to read from 04H and 05H
(see t
RLDV
).
rd_n
Low to Data Valid
(Only for Registers 02H, 04H, 05H)
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
0 ns
16 MHz
10 MHz
8 MHz
—
—
—
—
—
—
—
—
—
—
t
RLRH
40 ns
—
t
RLDV
0 ns
55 ns
t
RLDV1
rd_n
Low Data to Data Valid (for all Registers
except 02H, 04H, 05H)
for Read Cycle without a Previous Write
—
1.5 t
MCLK
+ 100 ns
t
RLDV1
rd_n
Low Data to Data Valid (for all Registers
except 02H, 04H, 05H)
for Read Cycle with a Previous Write
Data Float after
rd_n
High
cs_n
Low to
ready
Setup
(Load Capacitance on the ready
Output = 50 pF, V
OL
= 1.0 V)
cs_n
Low to
ready
Setup
(Load Capacitance on the ready
Output = 50 pF, V
OL
= 0.45 V)
wr_n
or
wrh_n
Low to
ready
Float for a Write
Cycle if No Previous Write is Pending
—
3.5 t
MCLK
+ 100 ns
t
RHDZ
0 ns
45 ns
—
32 ns
t
CLYV
—
40 ns
t
WLYZ
—
145 ns
continued
. . .
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