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参数资料
| 型号： | IBM25405GP-3BA200C2 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 17/48页 |
| 文件大小： | 649K |
| 代理商： | IBM25405GP-3BA200C2 |
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PowerPC 405GP Embedded Controller
Data Sheet
Advance Information
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 24 of 48
galdsh5f
06/15/99 Preliminary
Pin Functional Description 35mm, 456-Ball Enhanced Plastic Ball Grid Array Package (Part 1 of 14)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k to 5V)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input, pull-up or pull-down required
Ball
Signal Name
Description
I/O
Type
Imped
ance
(
)
BHC
Notes
PCI Interface (Number of pins = 60)
A17
B16
C17
A18
D17
C18
B18
A20
B21
A23
D21
B22
B23
C22
C26
F25
K26
L23
M25
M23
N25
M26
N26
P24
R24
R23
P23
R25
T24
U26
T25
V26
PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31
PCI Address/Data Bus. Multiplexed address
and data bus
I/O
5V tolerant
3.3V PCI
B4
D19
F24
K24
R26
PCIC0[BE0]
PCIC1[BE1]
PCIC2[BE2]
PCIC3[BE3]
PCI C (bus command)
or
Byte enable
I/O
5V tolerant
3.3V PCI
B4
E26
PCIParity
PCI parity. Parity is even across PCIAD0:31
and PCIC0:3[BE0:3]. PCIParity is valid one
cycle after either an address or data phase.
The PCI device that drove PCIAD0:31 is
responsible for driving PCIParity on the next
PCI bus clock.
I/O
5V tolerant
3.3V PCI
B4
J24
PCIFrame
PCIFrame is driven by the current PCI bus
master to indicate beginning and duration of a
PCI access.
I/O
5V tolerant
3.3V PCI
B4
J23
PCIIRDY
PCIIRDY is driven by the current PCI bus
master. Assertion of PCIIRDY indicates that
the PCI initiator is ready to transfer data.
I/O
5V tolerant
3.3V PCI
B4
G26
PCITRDY
The target of the current PCI transaction drives
PCITRDY. Assertion of PCITRDY indicates
that the PCI target is ready to transfer data.
I/O
5V tolerant
3.3V PCI
B4
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