参数资料
型号: IBM25PPC750FX-DB0122T
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 600 MHz, RISC PROCESSOR, CBGA292
封装: 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292
文件页数: 15/62页
文件大小: 452K
代理商: IBM25PPC750FX-DB0122T
DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
3. Electrical and Thermal Characteristics
Page 20 of 63
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3.6.1 IEEE 1149.1 AC Timing Specications
The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST. Unless otherwise noted, JTAG specifications
are referenced to GND and OVDD. The JTAG I/Os are powered by OVDD.
Table 3-9. JTAG AC Timing Specications (Independent of SYSCLK)
See Table 3-2 on page 10 for operating conditions.
Num
Characteristic
Min.
Max.
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
ns
2
TCK clock pulse width measured at 1.1V
15
ns
3
TCK rise and fall times
0
2
ns
4
Specification obsolete, intentionally omitted
5
TRST assert time
25
ns
1
6
Boundary-scan input data setup time
0
ns
2
7
Boundary-scan input data hold time
13
ns
2
8
TCK to output data valid
8
ns
3, 5
9
TCK to output high impedance
3
19
ns
3, 4
10
TMS, TDI data setup time
0
ns
11
TMS, TDI data hold time
15
ns
12
TCK to TDO data valid
2.0
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
14
TCK to output data invalid (output hold)
0
ns
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specication guaranteed by characterization and not tested.
Figure 3-7. JTAG Clock Input Timing Diagram
1
2
3
VM
TCK
VM
VM = Midpoint Voltage (OVDD/2)
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