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| 型号： | IBM25PPC750FX-DB0122T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 600 MHz, RISC PROCESSOR, CBGA292 |
| 封装： | 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件页数： | 28/62页 |
| 文件大小： | 452K |
| 代理商： | IBM25PPC750FX-DB0122T |
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DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
5. System Design Information
Page 32 of 63
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
After both PLLs are running and locked, the processor frequency can be toggled with very low latency.
For example, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock.
HID1[PS] can be reset to 0, causing the processor clock source to transition from PLL1 back to PLL0. If
PLL0 will not be needed for some time, it can be configured to be off while not in use. This is done by
resetting the HID1[PC0] field to 0, and setting HID1[PI0] to 1. Turning the non-selected PLL off results in
a modest power savings, but introduces added latency when changing frequency. If PLL0 is configured to
be off, the procedure for switching to PLL0 as the selected PLL involves changing the configuration and
range bits, waiting for lock, and then selecting PLL0, as described in the previous paragraph.
5.1.1 Restrictions and Considerations for PLL Conguration
Avoid the following when reconfiguring the PLLs:
1. The conguration and range bits in HID1 should only be modied for the non-selected PLL, since it will
require time to lock before it can be used as the source for the processor clock.
2. The HID1[PI0] bit should only be modied when PLL0 is not selected.
3. Whenever one of the PLLs is recongured, it must not be selected as the active PLL until enough time
has elapsed for the PLL to lock.
4. At all times, the frequency of the processor clock, as determined by the various conguration settings,
must be within the specication range for the current operating conditions.
5. Never select a PLL that is in the ‘off’ conguration.
5.1.1.1 Conguration Restriction on Frequency Transitions
It is considered a programming error to switch from one PLL to the other when both are configured in a
half-cycle multiplier mode. For example, with PLL0 configured in 9:2 mode (cfg = 01001) and PLL1 config-
ured in 13:2 mode (cfg = 01101), changing the select bit (HID1[PS]) is not allowed. In cases where such a
pairing of configurations is desired, an intermediate full-cycle configuration must be used between the two
half-cycle modes. For example, with PLL0 at 9:2, PLL1, configured at 6:1 is selected, then PLL0 is reconfig-
ured at 13:2, locked and selected.
5.1.2 PLL_RNG[0:1] Denitions for Dual PLL Operation
The dual PLLs on the 750FX are configured by the PLL_CFG[0:4] and PLL_RNG[0:1] signals. For a given
SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of opera-
tion. The PLL range configuration, for dual PLL operation, for the 750FX is shown in the following table.
Table 5-1. PLL_RNG [0:1] Denitions for Dual PLL Operation
PLL_RNG[0:1]
PLL Frequency Range
00
600 MHz and above
10
Below 600 MHz
01
Reserved
11
Reserved
相关PDF资料 |
PDF描述 |
|---|---|
| IBM25PPC750FX-DB1013T | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA292 |
| IBM25PPC750FX-GB0112T | 32-BIT, 600 MHz, RISC PROCESSOR, CBGA292 |
| IBM25PPC750FX-DB0513T | 32-BIT, 700 MHz, RISC PROCESSOR, CBGA292 |
| IBM25PPC750FX-FB0533T | 32-BIT, 700 MHz, RISC PROCESSOR, CBGA292 |
| IBM25PPC750FX-FB0112T | 32-BIT, 600 MHz, RISC PROCESSOR, CBGA292 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IBM25PPC750FX-FB1013T | 制造商:IBM 功能描述:32-BIT, 733 MHZ, RISC PROCESSOR, CBGA292 |
| IBM25PPC750FX-FB2513T | 制造商:IBM 功能描述:32-BIT, 800 MHz, RISC PROCESSOR, CBGA292 |
| IBM25PPC750FX-GB0122V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FX-GB0132T | 制造商:IC'S/TRANSISTORS/DIO 功能描述: 制造商:IC'S/TRANSISTORS/DIODES 功能描述: |
| IBM25PPC750FX-GB0132V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
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