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| 型号： | IBM25PPC750FX-DB0513T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 700 MHz, RISC PROCESSOR, CBGA292 |
| 封装： | 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件页数： | 9/62页 |
| 文件大小： | 452K |
| 代理商： | IBM25PPC750FX-DB0513T |
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DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 15 of 63
3.4 60x Bus Input AC Specications
Figure 3-3 provides the input timing diagram for the 750FX.
Table 3-7. 60x Bus Input Timing Specications
See Table 3-2 on page 10 for operating conditions.1,5
Num
Characteristic
1.8V Mode
2.5V Mode
3.3V Mode
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
10a
All inputs valid to SYSCLK (input setup)
1.0
—
1.5
1.8
—
ns
—
10b
INT_, SMI_, MCP, TBEN, DRTRY, and TLBISYNC
(input setup)
1.5
1.8
10c
Mode select input setup to HRESET
(TLBISYNC, DRTRY)
8—8—8—
tSYSCLK 2, 3, 4, 5
11a
SYSCLK to inputs invalid (input hold)
0.65
—
0.65
—
0.55
—
ns
6
11b
INT_, SMI_, MCP, TBEN, DRTRY, and TLBISYNC
(input hold)
1.5
2.5
ns
11c
HRESET to mode select input hold
(TLBISYNC, DRTRY)
0
—
0
—
0
—
ns
2, 4, 5
VM
Measurement Reference Voltage for Inputs
OVDD/2
—
Notes:
1. Input specifications are measured from the VM of the signal in question to VM of the rising edge of the input SYSCLK. Input and
output timings are measured at the pin (see Figure 3-3).
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-4 on page 16).
3. tSYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. This specication is for conguration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
5. All values are guaranteed by design, and are not tested.
Figure 3-3. Input Timing Diagram
VMsysclk(0.65V)
SYSCLK
ALL INPUTS
VM = Midpoint Voltage (OVDD/2)
10b
10a
11a
VM
11b
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