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| 型号： | IBM25PPC750GXEBB6572T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封装： | 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件页数： | 10/74页 |
| 文件大小： | 1054K |
| 代理商： | IBM25PPC750GXEBB6572T |
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Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Electrical and Thermal Characteristics
Page 18 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
3.3 Clock AC Specifications
Table 3-7 provides the clock AC timing specifications as defined in Figure 3-1.
Table 3-7. Clock AC Timing Specifications
Figure 3-1
Timing
Reference
Characteristic
Value
Unit
Notes
Min.
Max.
Processor frequency
500
1000
MHz
SYSCLK frequency
25
200
MHz
1
SYSCLK cycle time
5.0
40
ns
2, 3
SYSCLK slew rate
1.0
4.0
V/ns
4
SYSCLK duty cycle measured at 0.65 V
25
75
%
SYSCLK cycle-to-cycle jitter
—
±150
ps
Internal PLL relock time
—
100
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies.
Refer to the PLL_CFG[0:4] signal description in Table 5-2, 750GX Microprocessor PLL Configuration, on page 48 for valid
PLL_CFG[0:4] settings.
2. Slew rate for the SYSCLK inputs is measured from 0.4 to 1.0 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. See Section 3.4, Spread Spectrum Clock Generator, on page 19 for long-term jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that hard reset (HRESET)
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
6. Lower voltage and frequency operation will be available based on characterization results. See the IBM PowerPC 750GX RISC
Microprocessor Supplement for more information.
Figure 3-1. SYSCLK Input Timing Diagram
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
VM-SYSCLK: 0.65 V
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相关代理商/技术参数 |
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|---|---|
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