- 您现在的位置：买卖IC网 > PDF目录136444 > IBM25PPC750GXEBB6572T 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 PDF资料下载
参数资料
| 型号： | IBM25PPC750GXEBB6572T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封装： | 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件页数： | 13/74页 |
| 文件大小： | 1054K |
| 代理商： | IBM25PPC750GXEBB6572T |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Electrical and Thermal Characteristics
Page 20 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
3.5 60x Bus Input AC Specifications
Table 3-8 provides the 60x bus AC timing specifications defined in Figure 3-4 and Figure 3-5 on page 22.
3.5.1 Input Setup Timing
The information in this subsection is provided to clarify the criteria used to establish the timings in Table 3-8.
The DC Electrical Specifications shown in Table 3-4 on page 16 are not altered by this clarification. The valid
input signal levels remain VIH and VIL.
The input setup times shown as 10a in Table 3-8 specify the required time from the input signal crossing VM
to the rising edge of SYSCLK crossing VM.
For the timings in Table 3-8 to be valid, the falling edge of the input signal shown in Table 3-8 is assumed to
transition through VM and cross VIL-AC at the slew rate specified in Table 3-8. Input signals that do not reach
the VIL-AC boundary, or slew from VM to VIL-AC more slowly than specified, will result in longer input setup
times.
In the same way, on the rising edge, the input signal must continue past VM and cross the VIH-AC boundary
within the specified minimum slew rate. Input signals that do not reach the VIH-AC boundary within the slew
rate specified will result in longer input setup times.
Figure 3-4 provides the input timing diagram for the 750GX.
Table 3-8. 60x Bus Input AC Timing Specifications
See Table 3-2 on page 15 for operating conditions.1, 5, 6
Figure 3-4
and 3-5
Timing
Reference
Characteristic
1.8 V Mode
2.5 V Mode
3.3 V Mode
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
10a
Input setup: SYSCLK to inputs valid.
1.0
—
1.1
—
1.6
—
ns
10c
Mode select input setup to HRESET (TLBI-
SYNC, DRTRY, L2_TSTCLK, DBDIS,
QACK, and DBWO)
8—
8
—
8—
sysclk
cycles
11a
Input hold: SYSCLK to inputs invalid
0.45
—
0.3
—
0.3
—
ns
11c
HRESET to mode select input hold (TLBI-
SYNC, DRTRY, L2_TSTCLK, DBDIS,
QACK, and DBWO)
040
404
sysclk
cycles
VM
Measurement reference voltage for inputs
OVDD/2
—
VIL-AC
AC timing reference levels
—0.2
VIH-AC
OVDD - 0.2
—OVDD - 0.2
—
Slew Rate Reference input slew rate
1.0
—
1.5
—
2.0
—
V/ns
Notes:
1. Input specifications are measured from the midpoint voltage (VM) of the signal in question to the VM of the rising edge of the input
SYSCLK. Timings are measured at the pin (see Figure 3-4 on page 21).
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-5 on page 22).
3. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the
period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
5. All values are guaranteed by design, and are not tested.
6. Refer to Section 3.5.1 on page 20 and Figure 3-3 on page 21 for input setup timing definitions.
7. Input reference signal levels used to establish the timings defined in this table.
相关PDF资料 |
PDF描述 |
|---|---|
| ISL8705IBZ | DSP-ADDRESS SEQUENCER, PDSO14 |
| ICS932S208DG | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| IDT79R3041-20JG | 32-BIT, 20 MHz, RISC PROCESSOR, PQCC84 |
| ICS950902DFLFT | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS843207CY-350 | 375 MHz, OTHER CLOCK GENERATOR, PQFP48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IBM25PPC750GXECB2563T | 制造商:IBM 功能描述: |
| IBM25PPC750GXECB2H33T | 制造商:IBM 功能描述: |
| IBM25PPC750GXECB5H42V | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA GRE2 ? HALFMODE 933MH - Trays |
| IBM25PPC750GXECB5H82T | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA GRE2 LP HALFMODE 933 - Trays |
| IBM25PPC750GXECB5H82V | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA GRE2 LP HALFMODE 933 - Trays |
发布紧急采购，3分钟左右您将得到回复。