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参数资料
| 型号： | ICS1524AMLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN SSTL_3/PECL 24-SOIC |
| 产品变化通告： | Product Discontinuation 09/Feb/2012 |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率合成器，时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | LVTTL，晶体 |
| 输出： | PECL，SSTL-3 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 250MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | 1524AMLFT |
15
ICS1524A
ICS1524A Rev F 05/13/10
Specific Layout Guidelines
1. Digital Supply (VDD) – Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-F capacitor, located as close as possible to the pins. A
0.01-F capacitor may be added for additional high frequency rejection.
2. External Loop Filter – Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9
(EXTFIL and EXTFILRET) as possible with minimum length traces. Typical loop filter values are 6.8K Ohms for the
series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see
the Frequently Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.) A ground isolated, surface
trace can be useful to isolate this section from the rest of the board.
3. Analog PLL Supply (VDDA) – Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end
of the bead with 4.7-F. Bypass pin 10 to pin 11 (VSSA) with a 0.1-F capacitor. A 0.01-F capacitor may be added for
additional high frequency rejection. Locate these components as close as possible to the pins.
4. PECL Current Set Resistor – Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to
ground with a 0.1 -F capacitor.
5. PECL Outputs – Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ohm
characteristic impedance. Locate any optional series “snubbing” resistors as close as possible to the source pins. If
the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the
power and ground planes.
[These termination resistors are omitted if the load device implements them internally. For details, see the ICS applica-
tion note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on
Designing a Custom Interface for the ICS1523 (1523AN4.)]
6. Output Driver Supply – Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-F capacitor, located as close as possible
to the pins. A 0.01-F capacitor may be added for additional high frequency rejection.
7. SSTL_3 Outputs – SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmis-
sion line system at higher-output frequencies. With terminated outputs, the considerations of item 5, “PECL Outputs”
apply. See JEDEC documents JESD8-A and JESD8-8.
.
General Layout Guidelines
Use a PC board with at least four layers: one power, one ground, and two signal.
Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling.
All supply voltages must be supplied from a common source and must ramp together.
Any flux or other board surface debris can degrade the performance of the external loop filter.
Ensure that the 1524A area of the board is free of contaminants.
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相关代理商/技术参数 |
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| ICS1524AMT | 功能描述:IC CLK GEN SSTL_3/PECL 24-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS1524M | 制造商:ICS 制造商全称:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524MT | 制造商:ICS 制造商全称:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1526 | 制造商:ICS 制造商全称:ICS 功能描述:Video Clock Synthesizer |
| ICS1526G | 功能描述:IC VIDEO CLK SYNTHESIZER 16TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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