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型号： ICS1893AFILF
厂商： IDT, Integrated Device Technology Inc
文件页数： 70/136页
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
标准包装： 30
系列： PHYceiver™
类型： PHY 收发器
规程： MII
电源电压： 3.14 V ~ 3.47 V
安装类型： 表面贴装
封装/外壳： 48-BSSOP（0.295"，7.50mm 宽）
供应商设备封装： 48-SSOP
包装： 管件
其它名称： 1893AFILF
Chapter 7
Functional Blocks
ICS1893AF, Rev. D 10/26/04
October, 2004
39
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
The ISO/IEC-defined priority table determines the established link type. As a simpler alternative, the STA
can read the QuickPoll Detailed Status Register and determine the link type from the Data Rate bit (bit
17.15) and the Duplex bit (bit 17.14). For convenience, the QuickPoll Register also includes the Link Status
bit (bit 17.0) and the Auto-Negotiation Complete bit (bit 17.4).
If (1) the auto-negotiation process does not complete, or (2) the link is not established, or (3) both the
auto-negotiation process does not complete and the link is not established, then the STA can determine the
cause of the link failure by using the outputs of the ICS1893AF Auto-Negotiation Progress Monitor.
The Auto-Negotiation Progress Monitor provides the STA with four status bits of data to indicate both the
history and the present state of the auto-negotiation process. This status data is provided in the QuickPoll
Detailed Status register by using the Auto-Negotiation Complete bit (bit 17.4) as well as bits 17.13:11. The
bit order, from most-significant bit to least-significant bit, is 17.4, 17.13, 17.12, and 17.11. Using these four
bits, the Auto-Negotiation Progress Monitor provides nine state codes detailing the operation of the
auto-negotiation process for the STA. [For more information, see Section 8.12.3, “Auto-Negotiation
Progress Monitor (bits 17.13:11)”.]
The nine Auto-Negotiation Progress Monitor state codes are 0h through 8h and Fh. The Auto-Negotiation
Progress Monitor automatically latches the values of the Auto-Negotiation Arbitration State Machine into
the status bits only if the value of the present state is greater than the value that is currently in the status
bits.
For example, if the status bits have a value of 3h and the auto-negotiation process moves into:
State 1, the Auto-Negotiation Progress Monitor does not update the status bits to indicate the new state.
State 5, the Auto-Negotiation Progress Monitor updates the status bits to indicate the new state, State 5.
In this case, the status bits increase in value until either the auto-negotiation process successfully
completes or the STA reads the Auto-Negotiation Progress Monitor status bits.
When the STA reads the status bits, the present state of the auto-negotiation process is automatically
latched into the status bits, regardless of how they compare to the value currently in the latch. However,
the read presents the STA with the previously latched values of the status bits, not the values just latched
into the status register by the read. Therefore, the STA must perform two reads of the status bits to
determine the present state of the Auto-Negotiation Arbitration State Machine.
The first read provides a ’history’ of the auto-negotiation process, (that is, the highest state achieved by
the auto-negotiation process). The second read provides the present state of the auto-negotiation
process. This behavior allows management to determine the greatest forward progress made by the
auto-negotiation logic, which is valuable for diagnosing link errors and failures.
Note:
Once the auto-negotiation process completes successfully, the value of all the Progress Monitor
status bits and the Auto-Negotiation Complete bit have a value of logic one. A read operation of the
QuickPoll Register provides a value of logic one for the Auto-Negotiation Complete bit and an octal
value of 111 for the status bits.
Subsequent reads of the QuickPoll Register also provide a value of logic one for the
Auto-Negotiation Complete bit. However, the value of the status bits are 000b, providing the link
remains established.
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ICS1893AFILFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893AFIT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR)
ICS1893AFLF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOICN 包装:剪切带 (CT) 其它名称:ISL31470EIBZ-T7ACT
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR)
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