参数资料
型号: ICS1893BFLFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 88/133页
文件大小: 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
标准包装: 1
系列: PHYceiver™
类型: PHY 收发器
规程: MII
电源电压: 3.14 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 48-BSSOP(0.295",7.50mm 宽)
供应商设备封装: 48-SSOP
包装: 标准包装
产品目录页面: 1252 (CN2011-ZH PDF)
其它名称: 800-1017-6
ICS1893BF, Rev. F, 5/13/10
May, 2010
58
Chapter 7 Management Register Set
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.3.2 100Base-TX Full Duplex (bit 1.14)
The STA reads this bit to learn if the ICS1893BF can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.14 to logic:
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1893BF, the default value of bit
1.14 is logic one, in that the ICS1893BF supports 100Base-TX, full-duplex operations.)
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16: Extended
7.3.3 100Base-TX Half Duplex (bit 1.13)
The STA reads this bit to learn if the ICS1893BF can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.13 to logic:
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1893BF, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893BF supports 100Base-TX, half-duplex operations.)
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16:
7.3.4 10Base-T Full Duplex (bit 1.12)
The STA reads this bit to learn if the ICS1893BF can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.12 to logic:
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1893BF, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893BF
supports 10Base-T, full-duplex operations.)
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16:
7.3.5 10Base-T Half Duplex (bit 1.11)
The STA reads this bit to learn if the ICS1893BF can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.11 to logic:
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1893BF, the default value of bit 1.11
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893BF
supports 10Base-T, half-duplex operations.)
Bit 1.11 of the ICS1893BF Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
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ICS1893BFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器,接收器,收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC(0.295",7.50mm 宽) 供应商设备封装:16-SOIC 包装:带卷 (TR)
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