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参数资料
| 型号： | ICS1893BFLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 98/133页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 标准包装： | 1 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1252 (CN2011-ZH PDF) |
| 其它名称： | 800-1017-6 |
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Chapter 7 Management Register Set
ICS1893BF, Rev. F, 5/13/10
May, 2010
67
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.6.5 Technology Ability Field (bits 4.9:5)
When its Auto-Negotiation sublayer is enabled, the ICS1893BF transmits its link capabilities to its remote
link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine
the specific abilities that the ICS1893BF advertises. The ISO/IEC specification defines the TAF
technologies in Annex 28B.
The ISO/IEC specification reserves bits 4.12:10 for future use. When each of these reserved bits is:
Read by an STA, the ICS1893BF returns a logic zero
Written to by an STA, the STA must use the default value specified in this data sheet
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF,
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write
the default value of any reserved bits during all management register write operations.
Reserved bits 4.12:10 are Command Override Write (CW) bits. Whenever bit 16.15 (the Command
Register Override bit) is logic:
Zero, the ICS1893BF isolates all STA writes to CW bits, including bits 4.12:10.
One, an STA can modify the value of bits 4.12:10
Each of the bits 4.9:5 in the TAF represent a specific technology capability. When one of these bits is logic:
Zero, it indicates to the remote link partner that the local device cannot support the technology
represented by the bit.
One, it indicates to the remote link partner that the local device can support the technology.
With the exception of bit 4.9, the default settings of the TAF bits depend on the ICS1893BF operating
mode. Bit 4.9 is always logic zero, indicating that the ICS1893BF cannot support 100Base-T4 operations.
The TAF bits are Command Override Write bits. The default value of these bits depends on the signal level
on the HW/SW pin and whether the Auto-Negotiation sublayer is enabled.
With the Auto-Negotiation Enable bit (bit 0.12) set to logic:
Zero (that is, disabled), the ICS1893BF does not execute the auto-negotiation process. Upon completion
of the initialization sequence, the ICS1893BF proceeds to the Idle state and begins transmitting IDLES.
Two Control Register bits – the Data Rate Select bit (bit 0.13) and the Duplex Select bit (bit 0.8) –
determine the technology mode that the ICS1893BF uses for data transmission and reception. In this
mode, the values of the TAF bits (bits 4.8:5) are undefined.
One (that is, enabled), the ICS1893BF executes the auto-negotiation process and advertises its
capabilities to the remote link partner. The TAF bits (bits 4.8:5) determine the capabilities that the
ICS1893BF advertises to its remote link partner. For the ICS1893BF, all of these bits 4.8:5 are set to logic
one, indicating the ability of the ICS1893BF to provide these technologies.
Note:
1. The ICS1893BF does not alter the value of the Status Register bits based on the TAF bits in
register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the
capabilities of the ICS1893BF.
2. The STA can alter the default TAF bit settings, 4.12:5, and subsequently issue an Auto-Negotiation
Restart.
7.6.6 Selector Field (Bits 4.4:0)
When its Auto-Negotiation Sublayer is enabled, the ICS1893BF transmits its link capabilities to its remote
Link Partner during the auto-negotiation process. The Selector Field is transmitted based on the value of
bits 4.4:0. These bits indicate to the remote link partner the type of message being sent during the
auto-negotiation process. The ICS1893BF supports IEEE Std. 802.3, represented by a value of 00001b in
bits 4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A.
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相关代理商/技术参数 |
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| ICS1893BFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ICS1893BK | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| ICS1893BKI | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| ICS1893BKILF | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOICN 包装:剪切带 (CT) 其它名称:ISL31470EIBZ-T7ACT |
| ICS1893BKILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1 系列:- 类型:线路收发器 驱动器/接收器数:5/3 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:Digi-Reel® 产品目录页面:918 (CN2011-ZH PDF) 其它名称:296-25096-6 |
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