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参数资料
型号： ICS1893BKILFT
厂商： IDT, Integrated Device Technology Inc
文件页数： 103/133页
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 56-VQFN
标准包装： 1
系列： PHYceiver™
类型： PHY 收发器
规程： MII
电源电压： 3.14 V ~ 3.47 V
安装类型： 表面贴装
封装/外壳： 56-VFQFN 裸露焊盘
供应商设备封装： 56-VFQFP-EP（8x8）
包装： 标准包装
产品目录页面： 1252 (CN2011-ZH PDF)
其它名称： 800-1795-6
Chapter 7 Management Register Set
ICS1893BF, Rev. F, 5/13/10
May, 2010
71
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.8.2 Parallel Detection Fault (bit 6.4)
The ICS1893BF sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection
fault occurs when the ICS1893BF cannot disseminate the technology being used by its remote link partner.
Bit 6.4 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
7.8.3 Link Partner Next Page Able (bit 6.3)
Bit 6.3 is a status bit that reports the capabilities of the remote link partner to support the Next Page
features of the auto-negotiation process. The ICS1893BF sets this bit to a logic one if the remote link
partner sets the Next Page bit in its Link Control Word.
7.8.4 Next Page Able (bit 6.2)
Bit 6.2 is a status bit that reports the capabilities of the ICS1893BF to support the Next Page features of the
auto-negotiation process. The ICS1893BF sets this bit to a logic one to indicate that it can support these
features.
7.8.5 Page Received (bit 6.1)
The ICS1893BF sets its Page Received bit to a logic one whenever a new Link Control Word is received
and stored in its Auto-Negotiation link partner ability register. The Page Received bit is cleared to logic zero
on a read of the Auto-Negotiation Expansion Register.
Bit 6.1 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
7.8.6 Link Partner Auto-Negotiation Able (bit 6.0)
If the ICS1893BF:
Does not receive Fast Link Pulse bursts from its remote link partner, then this bit remains a logic zero.
Receives valid FLP bursts from its remote link partner (thereby indicating that it can participate in the
auto-negotiation process), then the ICS1893BF sets this bit to a logic one.
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相关代理商/技术参数
参数描述
ICS1893BKIT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893BKLF 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893BKLFT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893BKT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893BRIEF 制造商:ICS 制造商全称:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
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