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参数资料
型号： ICS1893BKLF
厂商： IDT, Integrated Device Technology Inc
文件页数： 132/133页
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 56-VQFN
标准包装： 260
系列： PHYceiver™
类型： PHY 收发器
规程： MII
电源电压： 3.14 V ~ 3.47 V
安装类型： 表面贴装
封装/外壳： 56-VFQFN 裸露焊盘
供应商设备封装： 56-VFQFP-EP（8x8）
包装： 管件
其它名称： 1893BKLF
800-1019
ICS1893BF, Rev. F, 5/13/10
May, 2010
98
Chapter 8 Pin Diagram, Listings, and Descriptions
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
MDIO
26
Input/
Output
Management Data Input/Output.
The signal on this pin can be tri-stated and can be driven by one of the
following:
A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893BF.
The ICS1893BF, to transfer status information.
All transfers and sampling are synchronous with the signal on the MDC
pin.
Note: If the ICS1893BF is to be used in an application that uses the
mechanical MII specification, MDIO must have a 1.5 k
±5%
pull-up resistor at the ICS1893BF end and a 2 k
±5% pull-down
resistor at the station management end. (These resistors enable
the station management to determine if the connection is intact.)
RXCLK
34
Output
Receive Clock.
The ICS1893BF sources the RXCLK to the MAC interface. The
ICS1893BF uses RXCLK to synchronize the signals on the following pins:
RXD[3:0], RXDV, and RXER. The following table contrasts the behavior
on the RXCLK pin when the mode for the ICS1893BF is either 10Base-T
or 100Base-TX.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Name
Pin
Number
Pin
Type
Pin Description
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893BF generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893BF generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the ICS1893BF
uses the REF_IN clock to
generate the RXCLK.
The ICS1893BF switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893BF is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
While the ICS1893BF is bringing
up a link, a clock phase change of
up to 360 degrees can occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
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ICS1893BKLFT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893BKT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
ICS1893BRIEF 制造商:ICS 制造商全称:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893BY-10 功能描述:PHYCEIVER LOW PWR 3.3V 64-TQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR)
ICS1893BY-10LF 功能描述:PHYCEIVER LOW PWR 3.3V 64-TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR)
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