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参数资料
| 型号： | ICS2509CYG-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24 |
| 文件页数： | 4/10页 |
| 文件大小： | 304K |
| 代理商： | ICS2509CYG-T |
3
ICS2509C
0008D—03/31/03
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . AVCC < (Vcc + 0.7V)
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . 4.3 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to Vcc +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - OUTPUT
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF; RL = 470 Ohms (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
RDSP
VO = VDD*(0.5)
36
Output Impedance
RDSN
VO = VDD*(0.5)
32
Output High Voltage
VOH
IOH = -8 mA
2.4
2.9
V
Output Low Voltage
VOL
IOL = 8 mA
0.25
0.4
V
VOH = 2.4 V
-26
-13.6
VOH = 2.0 V
-37
-22
VOL = 0.8 V
19
25
VOL = 0.55 V
13
17
Rise Time
1
Tr
VOL = 0.8 V, VOH = 2.0 V
0.5
1.4
2.1
ns
Fall Time
1
Tf
VOH = 2.0 V, VOL = 0.8 V
0.5
1.5
2.7
ns
Duty Cycle
1
Dt
VT = 1.5 V;CL=30 pF
45
50
55
%
at 66-100 MHz ; loaded outputs
52
100
at 133 MHz ; loaded outputs
39
75
Absolute Jitter
1
Tjabs
10000 cycles; CL = 30 pF
57
ps
Skew
1
Tsk
VT = 1.5 V (Window) Output to Output
80
150
ps
Phase error
1
Tpe
VT = Vdd/2; CLKIN-FBIN
-150
40
150
ps
Phase error Jitter
1
Tpe
3
VT = Vdd/2; CLKIN-FBIN; Delay Jitter
-50
35
50
ps
Delay Input-Output
1
DR1
VT = 1.5 V; PLL_EN = 0
3.3
3.7
ns
1 Guaranteed by design, not 100% tested in production.
Cycle to Cycle jitter
1
Tcyc-cyc
ps
Output High Current
Output Low Current
IOH
IOL
mA
ICS2509C
3.3V Phase-Lock Loop Clock Driver
TSD
IDT / ICS 3.3V Phase-Lock Loop Clock Driver
ICS2509C
3
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