- 您现在的位置：买卖IC网 > PDF目录61068 > ICS426GLFT (INTEGRATED DEVICE TECHNOLOGY INC) 156.25 MHz, OTHER CLOCK GENERATOR, PDSO16 PDF资料下载
参数资料
| 型号： | ICS426GLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 156.25 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 3/6页 |
| 文件大小： | 84K |
| 代理商： | ICS426GLFT |
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
3
Revision 091102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
ICS426
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS426 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -18pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 20 pF
load capacitance, each crystal capacitor would be 4 pF
[(20-18) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS426. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS448G-16 | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS448G-16T | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS501A-DPK | 200 MHz, OTHER CLOCK GENERATOR, UUC |
| ICS501AMI | 166 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS501AMLF | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS426GT | 制造商:ICS 制造商全称:ICS 功能描述:Serial ATA/Fibre Channel Clock Synthesizer |
| ICS43001AI22L | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS43002A01L | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS43002A40 | 制造商:ICS 制造商全称:ICS 功能描述:175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS43002A41 | 制造商:ICS 制造商全称:ICS 功能描述:700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
发布紧急采购，3分钟左右您将得到回复。