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参数资料
| 型号： | ICS426GLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 156.25 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 5/6页 |
| 文件大小： | 84K |
| 代理商： | ICS426GLFT |
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
5
Revision 091102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
ICS426
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70
°C
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70
° C
Note 1: Measured with 15 pF load.
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
°C
Power Supply Voltage (measured in respect to GND)
+3.13
+3.3
+3.46
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.13
3.3
3.47
V
Supply Current
IDD
No load
22
mA
Input High Voltage
VIH
OE, S0, S1
2
V
Input Low Voltage
VIL
OE, S0, S1
0.8
V
Output High Voltage
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12mA
0.4
V
Short Circuit Current
IOS
CLK output
±50
mA
On Chip Pull-up Resistor
RPU
OE, S0, S1
150
k
Input Capacitance
CIN
OE, S0, S1
5
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
FIN
Crystal or clock input
25
MHz
Output Clock Duty Cycle
Measured at VDD/2, Note 1
45
50
55
%
Output Rise Time
tOR
0.8 to 2.0V, Note 1
1
ns
Output Fall Time
tOF
2.0 to 0.8V, Note 1
1
ns
Short Term Jitter
peak to peak, Note 1
±70
ps
Long Term Jitter
Measured over 1000 cycles;
peak to peak, Note 1
170
ps
Phase Noise
106.25M CLK, relative to carrier,
100 Hz offset
-90
dBc/Hz
106.25M CLK, relative to carrier,
1kHz offset
-115
dBc/Hz
106.25M CLK, relative to carrier,
10 kHz offset
-121
dBc/Hz
106.25M CLK, relative to carrier,
100 kHz offset
-116
dBc/Hz
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