ICS507-01/02
PECL Clock Synthesizer
MDS 507 G
1
Revision 022002
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Packaged as 16 pin narrow SOIC
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 5 - 52 MHz
Enable usage of common low-cost crystal
Differential PECL output clock frequencies up
to 200 MHz
Duty cycle of 49/51
Operation voltage of 3.3 V or 5.0 V (±5%)
Ideal for SONET applications and oscillator
manufacturers
Advanced, low power CMOS process
Industrial temperature versions available
Available in die form
The ICS507-01 and ICS507-02 are inexpensive ways
to generate a low jitter 155.52 MHz (or other high
speed) differential PECL clock output from a low
frequency crystal input. Using Phase-Locked-Loop
(PLL) techniques, the devices use a standard
fundamental mode crystal to produce output clocks up
to 200 MHz.
Stored in each chip’s ROM is the ability to generate a
selection of different multiples of the input reference
frequency, including an exact 155.52 MHz clock from
common crystals. For lowest jitter and phase noise on
a 155.52 MHz clock, a 19.44 MHz crystal and the x8
selection can be used.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
timing, use the ICS527-02.
Description
Features
Block Diagram
GND
Crystal
or
clock
X1
X2
S0:1
Output
Buffer
Output
Buffer
PECL
62
270
270
62
VDD
RES
VDD
1.1k
2
Output Enable
(both outputs)
Output resistor values shown are for unterminated lines. Refer to MAN09 for additional information.
Clock Synthesis
and
Control Circuitry
Clock
Buffer/
Crystal
Oscillator