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参数资料
| 型号： | ICS548G-05T |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MULT T1/E1 16-TSSOP |
| 产品变化通告： | Product Discontinuation 13/May/2009 |
| 标准包装： | 2,500 |
| 类型： | 时钟/频率合成器，扇出缓冲器（分配） |
| PLL： | 带旁路 |
| 输入： | 时钟，晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:12 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 49.152MHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 3.15 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 548G-05T |
ICS548-05
T1/E1 CLOCK MULTIPLIER
CLOCK SYNTHESIZER
IDT T1/E1 CLOCK MULTIPLIER
3
ICS548-05
REV D 091511
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50
Ω trace (a commonly used trace
impedance), place a 33
Ω resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
Ω.
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS548-05 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F should be connected
between each VDD and GND on pins 3 and 5, as close
to the device as possible Other VDD’s can be
connected to pin 3. If reFOUT is not used, then REFEN
should be connected directly to ground.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(CL - 6) where C is the
load capacitor connected to X1 and X2, and CL is the
specified value of the load capacitance for the crystal. A
typical crystal CL is 18pF, so C = 2(18 - 6) = 24pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed. For a
clock input, leave X2 unconnected (floating).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI and obtain the best signal integrity,
the 33
Ω series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS548-05. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
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