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参数资料
| 型号： | ICS663MLF |
| 元件分类： | 时钟及定时 |
| 英文描述： | 663 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件页数： | 6/7页 |
| 文件大小： | 146K |
| 代理商： | ICS663MLF |
PLL BUILDING BLOCK
MDS 663 E
6
Revision 012006
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
ICS663
Determining the Loop Filter Values
The loop filter components consist of C1, C2, and RZ.
Calculating these values is best illustrated by an
example. Using the example in Figure 1, we can
synthesize 20 MHz from a 200 kHz input.
The phase locked loop may be approximately
described by the following equations:
Bandwidth
Damping factor,
where:
KO = VCO gain (MHz/Volt)
Icp = Charge pump current (A)
N = Total feedback divide from VCO,
including the internal VCO post divider
C1 = Loop filter capacitor (Farads)
RZ = Loop filter resistor (Ohms)
As a general rule, the bandwidth should be at least 20
times less than the reference frequency, i.e.,
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, RZ can
be determined since all other variables are known. In
the example of Figure 1, N = 200, comprising the divide
by 2 on the chip (VCO post divider) and the external
divide by 100. Therefore, the bandwidth equation
becomes:
and RZ = 25 k
Choosing a damping factor of 0.7 (a minimal damping
factor than can be used to ensure fast lock time),
damping factor equation becomes:
and C1 = 1.25 nF (1.2 nF is the nearest standard
value).
The capacitor C2 is used to damp transients from the
charge pump and should be approximately 1/20th the
size of C1, i.e.,
Therefore, C2 = 60 pF (56 pF nearest standard value).
To summarize, the loop filter components are:
C1 = 1.2 nf
C2 = 56 pf
Rz = 25 k
RZ KO ICP
()
2
π N
------------------------------------
=
ζ
RZ
2
------
KO ICP C1
N
-------------------------------
=
BW
REFIN
() 20
≤
10,000
RZ 200 2.5
2
π 200
--------------------------------
=
0.7
25 000
,
2
------------------
200 2.5 C1
200
---------------------------------
=
C2 C1 20
相关PDF资料 |
PDF描述 |
|---|---|
| ICS663MILF | 663 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS663MT | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS663M | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS664G-03LFT | 148.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664G-03T | 148.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS663MLFT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS663MT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS664-01 | 制造商:ICS 制造商全称:ICS 功能描述:Digital Video Clock Source |
| ICS664-02 | 制造商:ICS 制造商全称:ICS 功能描述:PECL Digital Video Clock Source |
| ICS664-03 | 制造商:ICS 制造商全称:ICS 功能描述:Digital Video Clock Source |
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