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参数资料
| 型号： | ICS673M-01LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 1/9页 |
| 文件大小： | 225K |
| 代理商： | ICS673M-01LF |
DATASHEET
PLL BUILDING BLOCK
ICS673-01
IDT / ICS PLL BUILDING BLOCK
1
ICS673-01
REV Q 071906
Description
The ICS673-01 is a low cost, high-performance Phase
Locked Loop (PLL) designed for clock synthesis and
synchronization. Included on the chip are the phase
detector, charge pump, Voltage Controlled Oscillator
(VCO), and two output buffers. One output buffer is a divide
by two of the other. Through the use of external reference
and VCO dividers (the ICS674-01), the user can customize
the clock to lock to a wide variety of input frequencies.
The ICS673-01 also has an output enable function that puts
both outputs into a high-impedance state. The chip also has
a power-down feature which turns off the entire device.
For applications that require low jitter or jitter attenuation,
see the MK2069.
Features
Packaged in 16-pin SOIC
Available in RoHS compliant package
Access to VCO input and feedback paths of PLL
Output operating range up to 120 MHz (5 V)
Able to lock MHz range outputs to kHz range inputs
through the use of external dividers
Output Enable tri-states outputs
Low skew output clocks
Power-down turns off chip
VCO predivide to feedback divider of 1 or 4
25 mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
Single supply +3.3 V (±5%) or +5 V (±10%) operating
voltage
Industrial and commercial temperature ranges
Forms a complete PLL, using the ICS674-01
For better jitter performance, use the MK1575
Block Diagram
REFIN
Phase/
Frequency
Detector
VCO
4
2
SEL
VCOIN
CHCP
UP
FBIN
DOWN
I
cp
I
cp
CLK2
VDD
MUX
1
0
External Feedback Divider
(such as the ICS674-01)
Clock Input
CAP
PD
(entire chip)
VDD
2
3
GND
CLK1
OE (both
outputs)
2
相关PDF资料 |
PDF描述 |
|---|---|
| ICS673M-01ILF | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS673M-01LFT | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS680G-01T | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS7151M-40LF | 133.4 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS7151M-50 | 16.7 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS673M-01LFT | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS673M-01T | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS674-01 | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Divider |
| ICS674R-01 | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS674R-01I | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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