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参数资料
| 型号： | ICS673M-01LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 6/9页 |
| 文件大小： | 225K |
| 代理商： | ICS673M-01LF |
ICS673-01
PLL BUILDING BLOCK
IDT / ICS PLL BUILDING BLOCK
6
ICS673-01
REV Q 071906
The CLK output frequency may be up to 2x the maximum
Output Clock Frequency listed in the AC Electrical
Characteristics above when the device is in an unlocked
condition. Make sure that the external divider can operate
up to this frequency.
Explanation of Operation
The ICS673-01 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The device
uses external PLL loop filter components which through
proper configuration allow for low input clock reference
frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling edges of
the clocks inputted to FBIN and REFIN. It then generates an
error signal to the charge pump, which produces a charge
proportional to this error. The external loop filter integrates
this charge, producing a voltage that then controls the
frequency of the VCO. This process continues until the
edges of FBIN are aligned with the edges of the REFIN
clock, at which point the output frequency will be locked to
the input frequency.
Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.
Figure 2. Using an External Comparator
to Reset the VCO
CHGP
VCOIN
R
S
C
S
C
P
CAP
+
-
R
4
R
2
R
3
PD
ICS673-01
REFIN
+3.3 or 5 V
SEL
VDD
0.01 F
FBIN
200 kHz
100
Digital Divider
such as ICS674-01
GND
CLK2
CAP
20 MHz
VCOIN
C
S
R
S
C
P
200 kHz
OE PD
40 MHz
CLK1
CHGP
相关PDF资料 |
PDF描述 |
|---|---|
| ICS673M-01ILF | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS673M-01LFT | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS680G-01T | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS7151M-40LF | 133.4 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS7151M-50 | 16.7 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS673M-01LFT | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS673M-01T | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS674-01 | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Divider |
| ICS674R-01 | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS674R-01I | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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