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| 型号： | ICS673M-01LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 673 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 5/9页 |
| 文件大小： | 225K |
| 代理商： | ICS673M-01LF |
ICS673-01
PLL BUILDING BLOCK
IDT / ICS PLL BUILDING BLOCK
5
ICS673-01
REV Q 071906
feedback divider begins to miss even more clock edges and
the VCO frequency is continually increased until it is running
at its maximum frequency. Whether caused by power supply
issues or by the external divider, the loop can only recover
by powering down the circuit or asserting PD.
The simplest way to avoid this problem is to use an external
divider that always operates correctly regardless of the VCO
speed. Figures 2 and 3 show that the VCO is capable of high
speeds. By using the internal divide-by-four and/or the
CLK2 output, the maximum VCO frequency can be divided
by 2, 4, or 8 and a slower counter can be used. Using the
ICS673 internal dividers in this manner does reduce the
number of frequencies that can be exactly synthesized by
forcing the total VCO divide to change in increments of 2, 4,
or 8.
If this lockup problem occurs, there are several solutions;
three of which are described below.
1. If the system has a reset or power good signal, this should
be applied to the PD pin, forcing the chip to stay powered
down until the power supply voltage has stabilized. If the
dividers are implemented in an FPGA or other circuit
configured on power-up, it is critical keep the ICS673
powered down until the dividers are working properly.
2. If no power good signal is available, a simple power-on
reset circuit can be attached to the PD pin, as shown in
Figure 1. When the power supply ramps up, this circuit holds
PD asserted (device powered down) until the capacitor
charges.
The circuit of Figure 1A is adequate in most cases, but the
discharge rate of capacitor C3 when VDD goes low is limited
by R1. As this discharge rate determines the minimum reset
time, the circuit of Figure 1B may be used when a faster
reset time is desired. The values of R1 and C3 should be
selected to ensure that PD stays below 1.0 V until the power
supply is stable.
3. A comparator circuit may be used to monitor the loop filter
voltage as shown in Figure 2. This circuit will dump the
charge off the loop filter by asserting PD if the VCO begins
to run too fast and the PLL can recover. A good choice for
the comparator is the National Semiconductor
LMC7211BIM5X. It is low power, version of the small
(SOT-23), low cost, and has high input impedance.
The trigger voltage of the comparator is set by the voltage
divider formed by R2 and R3. The voltage should be set to
a value higher than the VCO input is expected to run during
normal operation. Typically, this might be 0.5 V below VDD.
Hysteresis should be added to the circuit by connecting R4.
A. Basi c Ci r cui t
R
1
C
3
PD
I CS673- 01
VDD
B . Fast e r D i sch ar g e
R
1
C
3
PD
IC S 6 7 3 - 0 1
VD D
D
1
F i g 1 . P o we r o n Re s e t Ci r c u i t s
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相关代理商/技术参数 |
参数描述 |
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| ICS673M-01LFT | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS673M-01T | 功能描述:IC PLL BUILDING BLOCK 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS674-01 | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Divider |
| ICS674R-01 | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS674R-01I | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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