参数资料
型号: ICS8312AYLF
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/18页
文件大小: 0K
描述: IC CLK BUFF 1:12 250MHZ 32-LQFP
标准包装: 250
系列: HiPerClockS™
类型: 扇出缓冲器(分配)
电路数: 1
比率 - 输入:输出: 1:12
差分 - 输入:输出: 无/无
输入: LVCMOS,LVTTL
输出: LVCMOS,LVTTL
频率 - 最大: 250MHz
电源电压: 1.6 V ~ 3.465 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-TQFP(7x7)
包装: 托盘
产品目录页面: 1249 (CN2011-ZH PDF)
其它名称: 800-1111
8312AYLF
ICS8312
LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
IDT / ICS LVCMOS/LVTTL FANOUT BUFFER
10
ICS8312AY REV. D JULY 3, 2008
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependant on the input source and measurement equipment.
Additive Phase Jitter, 3.3V @ 100MHz
12kHz to 20MHz = 0.037ps (typical)
SSB
Phas
e
Noise
dBc/Hz
Offset from Carrier Frequency (Hz)
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