参数资料
型号: ICS8430S10BYI-02LFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/31页
文件大小: 0K
描述: IC CLK GENERATOR PLL 48TQFP
标准包装: 1,000
类型: 时钟/频率发生器,扇出缓冲器(分配),多路复用器
PLL:
主要目的: Cavium 处理器
输入: LVCMOS,LVDS,LVPECL,LVTTL,SSTL,晶体
输出: LVCMOS,LVDS,LVPECL,LVTTL
电路数: 1
比率 - 输入:输出: 2:10
差分 - 输入:输出: 是/是
频率 - 最大: 133.33MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-PTQFP-EP(7x7)
包装: 带卷 (TR)
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
18
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100
. This can also be
accomplished by removing R1 and making R2 50
. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
VCC
XTAL_OUT
XTAL_IN
R1
100
R2
100
Zo = 50 ohms
Rs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTAL_OUT
XTAL_IN
Zo = 50 ohms
C2
.1uf
LVPECL Driver
Zo = 50 ohms
R1
50
R2
50
R3
50
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