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| 型号： | ICS85104AGILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 85104 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 6.50 MM X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件页数： | 13/16页 |
| 文件大小： | 302K |
| 代理商： | ICS85104AGILF |
IDT / ICS 0.7V HCSL FANOUT BUFFER
6
ICS85104AGI REV. A MARCH 12, 2008
ICS85104I
LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter,
Integration Range: 12kHz - 20MHz at
100MHz = 0.22ps (typical)
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
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| ICS85104AMILF | 85104 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS85104AGILFT | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85105AGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 2:5 500MHZ 20TSSOP |
| ICS85105AGILF | 功能描述:IC CLOCK BUFFER MUX 2:5 20-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85105AGILFT | 功能描述:IC CLOCK BUFFER MUX 2:5 20-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85105AGIT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 2:5 500MHZ 20TSSOP |
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