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参数资料
| 型号： | ICS85108AGILFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER 1:8 500MHZ 24TSSOP |
| 标准包装： | 1,000 |
| 系列： | HiPerClockS™ |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:8 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 输出： | HCSL |
| 频率 - 最大： | 500MHz |
| 电源电压： | 2.97 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
ICS85108I Data Sheet
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK DISTRIBUTION CHIP
ICS85108AGI REVISION A OCTOBER 23, 2009
4
2009 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 5. HCSL AC Characteristics, VDD = VDDO = 3.3V ± 10%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at
≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range. See Parameter Measurement Information Section.
NOTE 7: Measurement taken from single-ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 14: Input duty cycle must be 50%.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
500
MHz
tPD
Propagation Delay; NOTE 1
1.5
3
ns
tsk(o)
Output Skew; NOTE 2, 3
80
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
400
ps
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
250MHz, Integration Range:
12kHz – 20MHz
0.09
ps
VRB
Ring-back Voltage Margin;
NOTE 5, 6
-100
100
mV
tSTABLE
Time before VRB is allowed;
NOTE 5, 6
500
ps
VMAX
Absolute Maximum Output
Voltage; NOTE 7, 8
1150
mV
VMIN
Absolute Minimum Output
Voltage; NOTE 7, 9
-300
mV
VCROSS
Absolute Crossing Voltage;
NOTE 7, 10, 11
250
550
mV
V
CROSS
Total Variation of VCROSS over
all edges; NOTE 7, 10, 12
140
mV
Rise/Fall Edge Rate;
NOTE 5, 13
Measured between -150mV to +150mV
0.6
5.5
V/ns
odc
Output Duty Cycle; NOTE 14
45
55
%
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