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| 型号： | ICS86953BYILFT-147 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件页数： | 10/13页 |
| 文件大小： | 262K |
| 代理商： | ICS86953BYILFT-147 |
86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
6
Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS86953I-147 provides sepa-
rate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
DDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 2
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each V
DDA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DDO
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
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