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| 型号： | ICS87016AYIT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 87016 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026ABC-HD, LQFP-48 |
| 文件页数： | 15/17页 |
| 文件大小： | 1191K |
| 代理商： | ICS87016AYIT |
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
IDT / ICS LVCMOS/LVTTL CLOCK GENERATOR
7
ICS87016AYI REV. B
MARCH 30, 2007
Table 5C. AC Characteristics, VDD = 3.3V±5%, VDDOx = 2.5V±5%, TA = -40°C to 85°C
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, VDD = 3.3V±5%, VDDOx = 1.8V±5%, TA = -40°C to 85°C
For NOTES, please see above, Table 5C.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tpLH
Propagation Delay,
Low to High
CLK0; NOTE 1A
2.9
3.5
4.0
ns
CLK1/CLK1; NOTE 1B
3.0
3.5
4.0
ns
tsk(b)
Bank Skew; NOTE 2, 6
Measured on the Rising Edge
50
ps
tsk(o)
Output Skew; NOTE 3, 6
Measured on the Rising Edge
170
ps
tsk(pp)
Part-to-Part Skew; NOTE 4, 6
800
ps
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
200
700
ps
odc
Output Duty Cycle
< 175MHz
45
55
%
≥ 175MHz
40
60
%
tEN
Output Enable Time; NOTE 5
10
ns
tDIS
Output Disable Time; NOTE 5
10
ns
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tpLH
Propagation Delay,
Low to High
CLK0; NOTE 1A
3.0
3.9
4.7
ns
CLK1/CLK1; NOTE 1B
3.0
3.9
4.7
ns
tsk(b)
Bank Skew; NOTE 2, 6
Measured on the Rising Edge
50
ps
tsk(o)
Output Skew; NOTE 3, 6
Measured on the Rising Edge
170
ps
tsk(pp)
Part-to-Part Skew; NOTE 4, 6
800
ps
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
200
700
ps
odc
Output Duty Cycle
< 175MHz
45
55
%
≥ 175MHz
40
60
%
tEN
Output Enable Time; NOTE 5
10
ns
tDIS
Output Disable Time; NOTE 5
10
ns
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